Methods of forming semiconductor device structures including stair step structures

• US 10,453,748 B2
• Filed: 08/27/2015
• Issued: 10/22/2019
• Est. Priority Date: 08/27/2015
• Status: Active Grant

• Current Assignee: Baker Hughes Incorporated (Baker Hughes Company), Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Park, Matthew, Olson, Adam L., Yu, Jixin
• Primary Examiner(s): Mazumder, Didarul A
• Application Number:
  US14/837,978
• Publication Number:
  US 20170062337A1
• Time in Patent Office: 1,517 Days
• Field of Search: 257773, 438618, 438666
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A method of forming a semiconductor device assembly comprises forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate. Portions of the tiers are selectively removed to form a stair step structure comprising a selected number of steps exhibiting different widths corresponding to variances in projected error associated with forming the steps. Contact structures are formed on the steps of the stair step structure. Semiconductor device structures and semiconductor devices are also described.

Claims

1. A method of forming a semiconductor device structure, comprising:

forming tiers comprising conductive structures and insulating structures in a stacked arrangement over a substrate;

selectively removing portions of the tiers to form a stair step structure consisting of exposed, recessed edges of the tiers defining steps to all receive contact structures thereon, at least some longitudinally intermediate steps of the stair step structure formed to exhibit relatively larger widths than at least some other of the steps of the stair step structure based on increases in error values of a mathematically modeled error distribution refined through empirical data on lateral sizes and positions of steps of a previously-formed, actual stair case structure effectuating formation of centrally-positioned contact structures thereon, the previously-formed, actual stair case structure having the same number of steps and overall width as the stair step structure; and

forming the contact structures on all of the steps of the stair step structure, at least a majority of the contact structures positioned at lateral centers of the steps thereunder.

2. The method of claim 1, wherein selectively removing portions of the tiers comprises:

forming a photoresist over the tiers; and

subjecting the photoresist and the tiers to a series of material removal processes to selectively remove different widths of the photoresist and the tiers based on different error values of the mathematically modeled error distribution.

3. The method of claim 2, wherein subjecting the photoresist and the tiers to a series of material removal processes to selectively remove different widths of the photoresist and the tiers based on different error values of the mathematically modeled error distribution comprises increasing amounts of the photoresist laterally removed by one of the series of material removal processes relative to previously laterally removed amounts of the photoresist based on an increase in an error value of the mathematically modeled error distribution associated with laterally sizing and positioning a step of the actual stair case structure to receive a centrally-positioned structure thereon relative to another error value of the mathematically modeled error distribution associated with laterally sizing and positioning another step of the actual stair case structure to receive another centrally-positioned contact structure thereon.

4. The method of claim 2, wherein subjecting the photoresist and the tiers to a series of material removal processes to selectively remove different widths of the photoresist and the tiers based on different error values of the mathematically modeled error distribution comprises removing relatively greater widths of the photoresist and at least some of the tiers during one or more sequentially later material removal processes than during one or more sequentially earlier material removal process according to an increase in at least one error value of the mathematically modeled error distribution associated with forming at least one relatively higher step of the actual stair case structure relative to at least one other error value of the mathematically modeled error distribution associated with forming at least one relatively lower step of the actual stair case structure.

5. The method of claim 2, wherein subjecting the photoresist and the tiers to a series of material removal processes to selectively remove different widths of the photoresist and the tiers based on different error values of the mathematically modeled error distribution comprises:

subjecting the photoresist and the tiers to a first material removal process comprising;

subjecting the photoresist to a first photolithographic process to remove a first width of the photoresist based on a first error value of the mathematically modeled error distribution; and

subjecting at least one of the tiers to at least one etching process to remove portions of the at least one of the tiers not covered by the photoresist following the first photolithographic process; and

subjecting the photoresist and the tiers to a second material removal process after the first material removal process, the second material removal process comprising;

subjecting the photoresist to a second photolithographic process following the at least one etching process to remove a second width of the photoresist different than the first width of the photoresist removed using the first photolithographic process, a magnitude of the second width based on a second error value of the mathematically modeled error distribution; and

subjecting at least two of the tiers to at least one additional etching process to remove portions of the at least two of the tiers not covered by the photoresist following the second photolithographic process.

6. The method of claim 5, wherein subjecting at least one of the tiers to at least one etching process to remove portions of the at least one of the tiers not covered by the photoresist comprises:

subjecting an insulating structure of a tier directly under the photoresist to a first anisotropic etch to remove a portion of the insulating structure corresponding to the first width; and

subjecting a conductive structure of the tier to a second anisotropic etch to remove a portion of the conductive structure corresponding to the first width.

7. The method of claim 6, wherein subjecting at least two of the tiers to at least one additional etching process to remove portions of the at least two of the tiers not covered by the photoresist comprises:

subjecting each of the insulating structure of the tier and another insulating structure of another tier directly under the tier to a third anisotropic etch to remove another portion of the insulating structure to the second width and a portion of the another insulating structure of the another tier to the first width; and

subjecting each of the conductive structure of the tier and another conductive structure of the another tier to a fourth anisotropic etch to remove another portion of the conductive structure to the second width and a portion of the another conductive structure of the another tier to the first width.

8. The method of claim 1, wherein forming the contact structures on the steps of the stair step structure comprises forming a first contact structure to be laterally spaced apart from a second contact structure laterally adjacent thereto by a different distance than that between the first contact structure and a third contact structure laterally adjacent thereto.

9. The method of claim 1, wherein forming the contact structures on the steps of the stair step structure comprises forming the contact structures to be non-uniformly spaced apart from one another.

10. The method of claim 1, wherein the mathematically modeled error distribution is generated through a stochastic modeling process designed to evaluate different process parameters employed to form the stair step structure.

11. The method of claim 1, wherein selectively removing portions of the tiers to form a stair step structure comprises forming each longitudinally higher step of the stair step structure to exhibit an increased width relative to a longitudinally lower step adjacent thereto in accordance with increases in sequential error values of the mathematically modeled error distribution.

12. The method of claim 2, wherein a magnitude of a width of the photoresist and the tiers removed by one of the series of material removal processes is at least 20 nanometers less than a magnitude of another width of the photoresist and the tiers removed by another of the series of material removal processes following the one of the series of material removal processes.

13. The method of claim 2, wherein a magnitude of a width of the photoresist and the tiers removed by one of the series of material removal processes is at least 50 nanometers greater than a magnitude of another width of the photoresist and the tiers removed by another of the series of material removal processes immediately preceding the one of the series of material removal processes.