Tone inversion method and structure for selective contact via patterning

• US 10,453,751 B2
• Filed: 02/14/2017
• Issued: 10/22/2019
• Est. Priority Date: 02/14/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Qiu, Xiaofeng, Aquilino, Michael V., Carpenter, Patrick D., Dechene, Jessica, Tang, Ming Hao, Huang, Haigou, Cao, Huy
• Primary Examiner(s): Nicely, Joseph C.
• Assistant Examiner(s): Koo, Lamont B
• Application Number:
  US15/432,016
• Publication Number:
  US 20180261510A1
• Time in Patent Office: 980 Days
• Field of Search: None
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/41725 Source or drain electrodes for field effect devices with monocrystalline semiconductor on source/drain region H01L29/0843
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A tone inversion method for integrated circuit (IC) fabrication includes providing a substrate with a layer of amorphous carbon over the substrate and a patterning layer over the amorphous carbon layer. The patterning layer is etched to define a first pattern of raised structures and a complementary recessed pattern that is filled with a layer of image reverse material. The first pattern of raised structures is then removed to define a second pattern of structures comprising the image reverse material. A selective etching step is used to transfer the second pattern into a dielectric layer disposed between the layer of amorphous carbon and the substrate.

Claims

1. A method for tone inversion for integrated circuit fabrication, the method comprising:

forming a plurality of gate stacks over a semiconductor substrate;

forming a spacer layer over sidewalls of the gate stacks;

forming a dielectric layer over the spacer layer and between adjacent gate stacks of the plurality of gate stacks;

forming a patterning structure over the plurality of gate stacks, the spacer layer and the dielectric layer, the patterning structure comprising, from bottom to top, an etch stop layer, an amorphous carbon layer, an adhesion layer, an amorphous silicon layer, an optional oxide layer, and a hard mask layer;

etching the hard mask layer, the optional oxide layer and the amorphous silicon layer to form a first pattern in the amorphous silicon layer;

forming a layer of image reverse material over the adhesion layer and laterally adjacent to the first pattern in the amorphous silicon layer, wherein the layer of image reverse material defines a second pattern complementary to the first pattern;

removing the amorphous silicon layer; and

using the image reverse material layer as a mask, etching the first pattern into the dielectric layer, wherein during etching of the dielectric layer a passivation layer comprising carbon from the amorphous carbon layer is deposited directly over the gate stacks and the spacer layers.

2. The method of claim 1, wherein the etch stop layer comprises silicon dioxide.

3. The method of claim 1, wherein the adhesion layer comprises SiCN.

4. The method of claim 1, wherein the hard mask layer comprises silicon nitride.

5. The method of claim 1, wherein the dielectric layer is etched selective to the spacer layer and the gate stack.

6. The method of claim 1, wherein the dielectric layer comprises silicon dioxide and the spacer layer comprises silicon nitride.

7. The method of claim 1, wherein the amorphous carbon layer thickness is 50 to 150 nm.

8. The method of claim 1, wherein the gate stacks are arranged at a pitch of less than 60 nm.

9. The method of claim 1, wherein the first pattern includes a critical dimension of less than 30 nm.

10. The method of claim 1, wherein the first pattern etched into the dielectric layer comprises a source/drain contact via.