Fan-out semiconductor package

• US 10,453,788 B2
• Filed: 05/24/2018
• Issued: 10/22/2019
• Est. Priority Date: 12/06/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jeong II, Lee, Jeong Ho, Kim, Jin Su, Cho, Bong Ju
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US15/988,893
• Publication Number:
  US 20190172781A1
• Time in Patent Office: 516 Days
• Field of Search: 257778
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49586 Insulating layers on lead frames
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers disposed on the insulating layers, and connection via layers penetrating through the insulating layers and electrically connecting the wiring layers to each other, and having a recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and an active surface of the semiconductor chip and including one or more redistribution layers electrically connecting the wiring layers and the connection pads to each other, in which the recess portion includes walls having different inclined angles.

Claims

1. A fan-out semiconductor package comprising:

a frame including a plurality of insulating layers, a plurality of wiring layers disposed on the plurality of insulating layers, and a plurality of connection via layers penetrating through the plurality of insulating layers and electrically connecting the plurality of wiring layers to each other, and having a recess portion;

a semiconductor chip having an active surface, on which connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion;

an encapsulant covering at least portions of the semiconductor chip and disposed in at least portions of the recess portion; and

a connection member disposed on the frame and the active surface of the semiconductor chip and including one or more redistribution layers electrically connecting the plurality of wiring layers of the frame and the connection pads of the semiconductor chip to each other,

wherein at least a portion of the recess portion is defined by a side wall and an inclined wall extending from the side wall.

2. The fan-out semiconductor package of claim 1, wherein the recess portion has a stopper layer disposed on a bottom surface thereof.

3. The fan-out semiconductor package of claim 2, wherein the stopper layer is a metal layer,

at least one of the plurality of wiring layers includes a ground, and

the metal layer is electrically connected to the ground.

4. The fan-out semiconductor package of claim 2, wherein a region of the stopper layer contacting the recess portion has a thickness smaller than that of an edge region of the stopper layer that does not contact the recess portion.

5. The fan-out semiconductor package of claim 2, wherein the stopper layer has a planar area larger than the inactive surface of the semiconductor chip.

6. The fan-out semiconductor package of claim 2, wherein the inactive surface of the semiconductor chip is attached to the stopper layer through an adhesive member.

7. The fan-out semiconductor package of claim 2, wherein at least one of the wiring layers are disposed on a level below the stopper layer.

8. The fan-out semiconductor package of claim 1, wherein the inclined wall has a first inclined angle and the side wall has a second inclined angle greater than the first inclined angle, and

the inclined wall is disposed to be closer to the connection member, as compared to the side wall.

9. The fan-out semiconductor package of claim 8, wherein the first inclined angle is an acute angle, and

the second inclined angle is a right angle.

10. The fan-out semiconductor package of claim 1, wherein the side wall has a third inclined angle and the inclined wall has a fourth inclined angle smaller than the third inclined angle, and

the side wall is disposed to be closer to the connection member, as compared to the inclined wall.

11. The fan-out semiconductor package of claim 10, wherein the third inclined angle is a right angle, and

the fourth inclined angle is an acute angle.

12. The fan-out semiconductor package of claim 1, wherein the at least a portion of the recess portion includes a wall having an acute angle and a wall having a right angle.

13. The fan-out semiconductor package of claim 1, wherein the plurality of insulating layers include a core insulating layer, one or more first build-up insulating layers disposed on a lower surface of the core insulating layer, and one or more second build-up insulating layers disposed on an upper surface of the core insulating layer, and

the core insulating layer has a thickness greater than that of each of the first and second build-up insulating layers.

14. The fan-out semiconductor package of claim 13, wherein the number of first build-up insulating layers is the same as the number of second build-up insulating layers.

15. The fan-out semiconductor package of claim 13, wherein the recess portion penetrates through at least a portion of the core insulating layer and penetrates through at least one of the one or more first and second build-up insulating layers.

16. The fan-out semiconductor package of claim 13, wherein first connection via layers penetrating through the one or more first build-up insulating layers and second connection via layers penetrating through the one or more second build-up insulating layers are tapered in opposite directions to each other.

17. The fan-out semiconductor package of claim 1, wherein a bottom surface of the recess portion has a planar area larger than the inactive surface of the semiconductor chip.

18. The fan-out semiconductor package of claim 1, wherein a lowermost wiring layer of the plurality of wiring layers is embedded in the frame so that a lower surface of the lowermost wiring layer is exposed.

19. The fan-out semiconductor package of claim 18, wherein the exposed lower surface of the lowermost wiring layer has a step with respect to a lower surface of the frame.

20. The fan-out semiconductor package of claim 1, wherein first metal bumps are disposed on the connection pads of the semiconductor chip, and

upper surfaces of the first metal bumps are coplanar with an upper surface of the encapsulant.

21. The fan-out semiconductor package of claim 20, wherein an upper surface of an uppermost wiring layer of the plurality of wiring layers of the frame or an upper surface of an uppermost connection via layer of the plurality of connection via layers is coplanar with the upper surfaces of the first metal bumps and the upper surface of the encapsulant.

22. The fan-out semiconductor package of claim 1, further comprising:

a first passivation layer disposed on the connection member and having openings exposing at least portions of the one or more redistribution layers;

underbump metal layers disposed in the openings of the first passivation layer and connected to at least portions of the exposed one or more redistribution layers; and

electrical connection structures disposed on the first passivation layer and connected to the underbump metal layers.

23. The fan-out semiconductor package of claim 22, further comprising a second passivation layer disposed on a lower surface of the frame and having openings exposing at least portions of a lowermost wiring layer of the plurality of wiring layers.

24. The fan-out semiconductor package of claim 1, wherein second metal bumps are disposed on an uppermost wiring layer of the plurality of wiring layers and are connected to the connection member.

25. The fan-out semiconductor package of claim 24, wherein surfaces of the second metal bumps in contact with the connection member is disposed on a level that is substantially the same as a level of a surface of the encapsulant in contact with the connection member.