Metal-on-metal capacitors
First Claim
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1. A capacitor structure comprising:
- an array of capacitor unit cells surrounded by a plurality of border unit cells;
each capacitor unit cell comprises a lower metal layer including a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes;
each border unit cell comprises a first plurality of dummy finger electrodes interdigitated with a second plurality of dummy finger electrodes in the lower metal layer; and
wherein the first and second plurality of finger electrodes are pitched-matched across the array of capacitor unit cells, and the first and second plurality of dummy finger electrodes are pitch-matched with the first and second plurality of finger electrodes.
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Abstract
Capacitor structures with pitch-matched capacitor unit cells are described. In an embodiment, the capacitor unit cells are formed by interdigitated finger electrodes. The finger electrodes may be pitch-matched in multiple metal layers within a capacitor unit cell, and the finger electrodes may be pitch-matched among an array of capacitor unit cells. Additionally, border unit cells may be pitch-matched with the capacitor unit cells.
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Citations
20 Claims
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1. A capacitor structure comprising:
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an array of capacitor unit cells surrounded by a plurality of border unit cells; each capacitor unit cell comprises a lower metal layer including a first plurality of finger electrodes interdigitated with a second plurality of finger electrodes; each border unit cell comprises a first plurality of dummy finger electrodes interdigitated with a second plurality of dummy finger electrodes in the lower metal layer; and wherein the first and second plurality of finger electrodes are pitched-matched across the array of capacitor unit cells, and the first and second plurality of dummy finger electrodes are pitch-matched with the first and second plurality of finger electrodes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A capacitor structure comprising:
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a lower metal layer including a first array of finger electrodes interdigitated with a second array of finger electrodes within a corresponding array of capacitor unit cells; an upper metal layer including a third array of finger electrodes interdigitated with a fourth array of finger electrodes within the array of capacitor unit cells, wherein the first and second arrays of finger electrodes are orthogonal to the third and fourth arrays of finger electrodes; wherein the first array of finger electrodes comprises a common lower rail extending through a first series of capacitor unit cells within the array of capacitor unit cells, wherein a corresponding series of the first array of finger electrodes and the third array of finger electrodes are electrically connected to the common lower rail; and wherein the fourth array of finger electrodes comprises a common upper rail extending through a second series of capacitor unit cells within the array of capacitor unit cell, and a corresponding series of the fourth array of finger electrodes and the second array of finger electrodes are electrically connected to the common upper rail. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A capacitor structure comprising:
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a lower metal layer including a first array of finger electrodes interdigitated with a second array of finger electrodes within a corresponding array of capacitor unit cells; an upper metal layer including a third array of finger electrodes interdigitated with a fourth array of finger electrodes within the array of capacitor unit cells; and a polysilicon layer below the lower metal layer, the polysilicon layer including a fifth array of finger electrodes interdigitated with a sixth array of finger electrodes; wherein the first, second, fifth, and sixth arrays of finger electrodes are orthogonal to the third and fourth arrays of finger electrodes. - View Dependent Claims (18, 19, 20)
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Specification