Method for fabricating glass substrate package

• US 10,453,819 B2
• Filed: 09/23/2018
• Issued: 10/22/2019
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Ping-Jung Yang
• Original Assignee: Ping-Jung Yang
• Inventors: Yang, Ping-Jung
• Primary Examiner(s): McFadden, Michael P
• Application Number:
  US16/139,040
• Publication Number:
  US 20190027459A1
• Time in Patent Office: 394 Days
• Field of Search: 361320, 361762
• CPC Class Codes: H01G 4/129 containing a glassy phase, e.g. glass ceramic
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/056 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05688 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/05788 Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2224/13076 being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32151 the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48228 : the bond pad being disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/48465 : the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 23/15 : Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/30 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05B 45/60 : Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
• CPC Class Codes: H05K 1/09 : Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H10K 77/10 : Substrates, e.g. flexible substrates
• CPC Class Codes: Y02E 10/549 : Organic PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Claims

1. A chip packaging structure comprising:

a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;

a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a first opening is in said first dielectric layer and exposed a top surface of said metal conductor, a second dielectric layer on said first dielectric layer, wherein a second opening is in said second dielectric layer and exposed said top surface of said metal conductor, said first opening and a top surface of said first dielectric layer, a first metal layer on said top surface of said metal conductor, on said a sidewall of said first opening, on said top surface of said first dielectric layer and on said sidewall of said second opening and a second metal layer on said first metal layer and in said first and second openings, wherein a top surface of said second metal layer, a top surface of said second dielectric layer, a top surface of said first metal layer are coplanar;

a second metal connection structure is under said second surface, wherein said second metal connection structure comprises a third dielectric layer on said second surface, wherein a third opening is in said third dielectric layer and exposed a bottom surface of said metal conductor, a third metal layer of said second metal connection structure on said third dielectric layer and in said third opening, a fourth metal layer of said second metal connection structure on said third metal layer and in said third opening and a fourth dielectric layer on said fourth metal layer, wherein a fourth opening in said fourth dielectric layer and exposed said fourth metal layer;

a topmost dielectric layer is over said first surface, over said first metal connection structure and on a fifth metal layer of said first metal connection structure, wherein a fifth opening in said topmost dielectric layer and exposed said fifth metal layer;

a first metal bump is under said second metal connection structure and under said fourth dielectric layer, wherein said first metal bump comprises a sixth metal layer and a seventh metal layer in said fourth opening and under said fourth dielectric layer; and

a first chip is over said topmost dielectric layer, wherein said first chip comprises a second metal bump connected to said first metal bump through said second metal layer, one of said metal conductors and said fourth metal layer.

2. The chip packaging structure of claim 1, wherein said first and second dielectric layers comprises an oxide layer.

3. The chip packaging structure of claim 1, wherein said first metal layer comprises titanium.

4. The chip packaging structure of claim 1, wherein said second metal layer comprises copper.

5. The chip packaging structure of claim 1, wherein said third dielectric layers comprises an oxide layer.

6. The chip packaging structure of claim 1, wherein said fourth dielectric layer comprises a polymer layer.

7. The chip packaging structure of claim 1, wherein said sixth metal layer comprises a titanium.

8. The chip packaging structure of claim 1, wherein said seventh metal layer comprises a copper.

9. The chip packaging structure of claim 1, wherein said seventh metal layer comprises a tin layer.

10. The chip packaging structure of claim 1 further comprising a discrete passive component mounted under said glass substrate and connected to said second metal connection structure.

11. The chip packaging structure of claim 1 further comprising a third metal bump under said second metal connection structure and under said fourth dielectric layer, wherein said second metal bump is connected to said first and third metal bumps through said first metal connection structure, multiple said metal conductors, said fourth metal layer.

12. A substrate structure comprising:

a glass substrate having a first surface and a second surface opposed to said first surface, wherein said first surface is parallel to said second surface, multiple metal conductors extending through said glass substrate beginning at said first surface and ending at said second surface, wherein one of said metal conductors comprises a cross-section surface parallel to said first surface, wherein said cross-section surface comprises a first edge, a second edge opposite to and substantially parallel with said first edge, a third edge and a fourth edge opposite to said third edge, wherein said first edge has a first length is greater than that of said third and fourth edges, wherein said second edge has a second length is greater than that of said third and fourth edges, wherein said metal conductors comprises a first sidewall, a second sidewall opposite to and substantially parallel with said first sidewall, a third sidewall and a fourth sidewall opposite to said third sidewall;

a first metal connection structure is on said first surface, wherein said first metal connection structure comprises a first dielectric layer on said first surface, wherein a first opening is in said first dielectric layer and exposed a top surface of said metal conductor, a second dielectric layer on said first dielectric layer, wherein a second opening is in said second dielectric layer and exposed said top surface of said metal conductor, said first opening and a top surface of said first dielectric layer, a first metal layer on said top surface of said metal conductor, on said a sidewall of said first opening, on said top surface of said first dielectric layer and on said sidewall of said second opening and a second metal layer on said first metal layer and in said first and second openings, wherein a top surface of said second metal layer, a top surface of said second dielectric layer, a top surface of said first metal layer are coplanar;

a second metal connection structure is under said second surface, wherein said second metal connection structure comprises a third dielectric layer on said second surface, wherein a third opening is in said third dielectric layer and exposed a bottom surface of said metal conductor, a third metal layer of said second metal connection structure on said third dielectric layer and in said third opening, a fourth metal layer of said second metal connection structure on said third metal layer and in said third opening and a fourth dielectric layer on a bottom surface of said fourth metal layer and on a sidewall of said third and fourth metal layers, wherein a fourth opening in said fourth dielectric layer and exposed said fourth metal layer; and

a topmost dielectric layer is over said first surface, over said first metal connection structure and on a fifth metal layer of said first metal connection structure, wherein a fifth opening in said topmost dielectric layer and exposed said fifth metal layer; and

a first metal bump is under said second metal connection structure and under said fourth dielectric layer, wherein said first metal bump comprises a sixth metal layer and a seventh metal layer in said fourth opening and under said fourth dielectric layer.

13. The substrate structure of claim 12 further comprising a second metal bump is under said second metal connection structure and under said fourth dielectric layer, wherein said fourth metal layer is connected to said multiple said metal conductors and said first and second metal bumps.

14. The substrate structure of claim 12, wherein said first, second and third dielectric layers comprise an oxide layer.

15. The substrate structure of claim 12, wherein said first and third metal layers comprises titanium.

16. The substrate structure of claim 12, wherein said second and fourth metal layers comprises copper.

17. The substrate structure of claim 12, wherein said fourth dielectric layers comprises a polymer layer.

18. The substrate structure of claim 12, wherein said seventh metal layer comprises a copper.

19. The substrate structure of claim 12 further comprises a discrete passive component mounted under said glass substrate and connected to said second metal connection structure.

20. The substrate structure of claim 12, wherein said second metal connection structure comprise a passive device between said fourth dielectric layer and said glass substrate.