Structure and method to form nanosheet devices with bottom isolation

• US 10,453,824 B1
• Filed: 05/08/2018
• Issued: 10/22/2019
• Est. Priority Date: 05/08/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mochizuki, Shogo, Yeung, Chun Wing
• Primary Examiner(s): Reames, Matthew L
• Application Number:
  US15/973,992
• Publication Number:
  US 20190348403A1
• Time in Patent Office: 532 Days
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02293 formation of epitaxial layers by a deposition process epitaxial growth per se C30B
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02603 Nanowires
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 25/071 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1029 of field-effect transistors
• CPC Class Codes: H01L 29/165 : in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 : fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 : with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method for manufacturing a semiconductor device includes forming a plurality of silicon germanium and silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer. The stacked configuration is patterned into a plurality of patterned stacks spaced apart from each other. The patterning forms a plurality of recessed portions in the substrate. In the method, the silicon germanium layers are etched to remove portions of the silicon germanium layers from exposed lateral sides of the silicon germanium layers, and inner spacer layers are formed in place of the removed portions. A plurality of lower epitaxial layers are grown in the recessed portions. A plurality of epitaxial source/drain regions are grown from the lower epitaxial layers and from exposed lateral sides of the silicon layers.

Claims

1. A method for manufacturing a semiconductor device, comprising:

forming a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a silicon layer stacked on a silicon germanium layer;

patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, wherein the patterning forms a plurality of recessed portions in the semiconductor substrate;

etching the plurality of silicon germanium layers to remove portions of the plurality of silicon germanium layers from exposed lateral sides of each of the plurality of silicon germanium layers;

forming an inner spacer layer in place of each of the removed portions of the plurality of silicon germanium layers;

growing a plurality of lower epitaxial layers in the plurality of recessed portions in a first epitaxial growth process, wherein the plurality of lower epitaxial layers have one or more edges aligned with outer edges of adjacent ones of the plurality of patterned stacks; and

growing a plurality of epitaxial source/drain regions adjacent the plurality of patterned stacks, wherein the plurality of epitaxial source/drain regions are grown from the plurality of lower epitaxial layers and from exposed lateral sides of the plurality of silicon layers in a second epitaxial growth process.

2. The method according to claim 1, wherein the first epitaxial process comprises a bottom-up growth process.

3. The method according to claim 2, wherein the first epitaxial process is performed using rapid thermal chemical vapor deposition epitaxial growth using at least one of SiH₄, GeH₄, CH₃SiH₃, B₂H₆, PF₃, and H₂ gases.

4. The method according to claim 3, wherein the first epitaxial process is performed at a temperature range of about 450°

C. to about 800°

C., and a pressure range of about 1 Torr-about 50 Torr.

5. The method according to claim 1, wherein the plurality of lower epitaxial layers are undoped.

6. The method according to claim 1, wherein the plurality of lower epitaxial layers are carbon (C) doped.

7. The method according to claim 1, wherein the plurality of lower epitaxial layers are counter doped with respect to a doping of the plurality of epitaxial source/drain regions.

8. The method according to claim 1, wherein the plurality of lower epitaxial layers are grown to a height that is level with or substantially level with a topmost surface of the substrate under the lowermost silicon germanium layers of the plurality of patterned stacks.

9. The method according to claim 1, further comprising:

selectively removing remaining portions of the plurality of silicon germanium layers from the plurality of patterned stacks; and

replacing the removed remaining portions of the plurality of silicon germanium layers with respective gate structures.

10. The method according to claim 1, wherein a dummy gate is formed on each of the plurality of patterned stacks, and the method further comprises replacing the dummy gate on each of the plurality of patterned stacks with a gate structure.

11. A semiconductor device, comprising:

a plurality of stacked structures spaced apart from each other on a substrate, wherein the plurality of stacked structures each comprise a plurality of gate structures and a plurality of channel layers;

a plurality of lower epitaxial layers in recessed portions of the substrate adjacent the plurality of stacked structures; and

a plurality of epitaxial source/drain regions extending from the plurality of channel layers and from the plurality of lower epitaxial layers;

wherein the plurality of lower epitaxial layers have one or more edges aligned with outer edges of adjacent ones of the plurality of stacked structures.

12. The semiconductor device according to claim 11, wherein the plurality of lower epitaxial layers are undoped.

13. The semiconductor device according to claim 11, wherein the plurality of lower epitaxial layers are carbon (C) doped.

14. The semiconductor device according to claim 11, wherein the plurality of lower epitaxial layers are counter doped with respect to a doping of the plurality of epitaxial source/drain regions.

15. The semiconductor device according to claim 11, wherein the plurality of lower epitaxial layers are at a height that is level with or substantially level with a topmost surface of the substrate under the plurality of stacked structures.

16. A method for manufacturing a semiconductor device, comprising:

forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a semiconductor substrate in a stacked configuration comprising a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer;

patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, wherein the patterning forms a plurality of recessed portions in the semiconductor substrate;

etching the plurality of first semiconductor layers to remove portions of the plurality of first semiconductor layers from exposed lateral sides of each of the plurality of first semiconductor layers;

forming an inner spacer layer in place of each of the removed portions of the plurality of first semiconductor layers;

growing a plurality of lower epitaxial layers in the plurality of recessed portions in a first epitaxial growth process, wherein the plurality of lower epitaxial layers have one or more edges aligned with outer edges of adjacent ones of the plurality of patterned stacks; and

growing a plurality of epitaxial source/drain regions adjacent the plurality of patterned stacks, wherein the plurality of epitaxial source/drain regions are grown from the plurality of lower epitaxial layers and from exposed lateral sides of the plurality of second semiconductor layers in a second epitaxial growth process.

17. The method according to claim 16, wherein the first epitaxial process comprises a bottom-up growth process.

18. The method according to claim 16, wherein the plurality of lower epitaxial layers are undoped.

19. The method according to claim 16, wherein the plurality of lower epitaxial layers are carbon (C) doped.

20. The method according to claim 16, wherein the plurality of lower epitaxial layers are counter doped with respect to a doping of the plurality of epitaxial source/drain regions.