Tuning tensile strain on FinFET
First Claim
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1. A semiconductor device comprising:
- a first device comprising;
a first fin;
first source/drain regions in the first fin on opposing sides of a first channel region;
a first gate electrode overlying the first channel region; and
a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having linear sidewalls; and
a second device comprising;
a second fin;
second source/drain regions in the second fin on opposing sides of a second channel region;
a second gate electrode overlying the second channel region; and
a second dielectric layer on opposing sides of the second gate electrode, the second dielectric layer being a contracted dielectric, the second gate electrode having convex sidewalls projecting toward concave sidewalls of the second dielectric layer.
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Abstract
A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
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Citations
20 Claims
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1. A semiconductor device comprising:
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a first device comprising; a first fin; first source/drain regions in the first fin on opposing sides of a first channel region; a first gate electrode overlying the first channel region; and a first dielectric layer on opposing sides of the first gate electrode, the first gate electrode having linear sidewalls; and a second device comprising; a second fin; second source/drain regions in the second fin on opposing sides of a second channel region; a second gate electrode overlying the second channel region; and a second dielectric layer on opposing sides of the second gate electrode, the second dielectric layer being a contracted dielectric, the second gate electrode having convex sidewalls projecting toward concave sidewalls of the second dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a first fin extending from a substrate; first source/drain regions in the first fin on opposing sides of a first channel region; a first gate over the first channel region; a contracted dielectric disposed over the first source/drain regions; first spacers interposed between the first gate and the contracted dielectric, the first spacers having a concave surface extending toward the contracted dielectric; a second fin extending from the substrate; second source/drain regions in the second fin on opposing sides of a second channel region; a second gate over the second channel region; a dielectric disposed over the second source/drain regions; and second spacers interposed between the second gate and the dielectric, the second spacers having a linear surface facing the dielectric. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A semiconductor device comprising:
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a first device comprising; a first fin; first source/drain regions in the first fin on opposing sides of a first channel region; a first gate electrode overlying the first channel region; and a first dielectric layer on opposing sides of the first gate electrode, the first dielectric layer being a contracted dielectric layer, the first gate electrode having convex sidewalls projecting toward concave sidewalls of the first dielectric layer; a second device comprising; a second fin; second source/drain regions in the second fin on opposing sides of a second channel region; a second gate electrode overlying the second channel region, sidewalls of the second gate electrode having a different shape than sidewalls of the first gate electrode; and a second dielectric layer on opposing sides of the second gate electrode, the second dielectric layer being uncontracted; and an interlayer dielectric layer over the first fin and the second fin, the interlayer dielectric layer extending along sidewalls of the first dielectric layer and the second dielectric layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification