Techniques for enhancing vertical gate-all-around FET performance
First Claim
1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:
- patterning at least one fin in a substrate;
forming bottom source and drains at a base of the at least one fin;
forming bottom spacers on the bottom source and drains;
forming a gate along sidewalls of the at least one fin;
recessing the gate to expose a top portion of the at least one fin;
forming a native oxide layer along the sidewalls of the top portion of the at least one fin;
depositing a charged layer over the at least one fin in direct contact with the native oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;
forming top spacers above the gate; and
forming top source and drains above the top spacers.
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Abstract
Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.
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Citations
8 Claims
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1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:
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patterning at least one fin in a substrate; forming bottom source and drains at a base of the at least one fin; forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the at least one fin; recessing the gate to expose a top portion of the at least one fin; forming a native oxide layer along the sidewalls of the top portion of the at least one fin; depositing a charged layer over the at least one fin in direct contact with the native oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification