Method of maintaining the state of semiconductor memory having electrically floating body transistor
First Claim
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1. A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include;
a first bipolar device having a first floating base region, a first collector, and a first emitter, anda second bipolar device having a second floating base region, a second collector, and a second emitter,wherein said first floating base region is common to said second floating base region,wherein said first collector is common to said second collector,wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors,wherein said first and second collectors are commonly connected to at least two of said memory cells; and
a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors.
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Abstract
Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.
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Citations
20 Claims
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1. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include; a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter, wherein said first floating base region is common to said second floating base region, wherein said first collector is common to said second collector, wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors, wherein said first and second collectors are commonly connected to at least two of said memory cells; and a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes; a first bipolar device having a first floating base region, a first collector, and a first emitter, and a second bipolar device having a second floating base region, a second collector, and a second emitter, wherein said first floating base region is common to said second floating base region, wherein said first collector is common to said second collector, wherein application of back-bias to said collector results in at least two stable floating base region charge levels, wherein said first and second collectors are commonly connected to at least two of said memory cells; and a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor memory array comprising:
a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes; a first bipolar device having a first floating base region, a first collector, and a first emitter; and a second bipolar device having a second floating base region, a second collector, and a second emitter; wherein said first floating base region is common to said second floating base region; wherein said first collector is common to said second collector; wherein states of said memory cells are maintained upon repeated read operations; and a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors. - View Dependent Claims (16, 17, 18, 19, 20)
Specification