Method of maintaining the state of semiconductor memory having electrically floating body transistor

• US 10,453,847 B2
• Filed: 05/07/2019
• Issued: 10/22/2019
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US16/404,964
• Publication Number:
  US 20190259763A1
• Time in Patent Office: 168 Days
• CPC Class Codes: G11C 11/04 using storage elements having cylindrical form, e.g. rod, wire G11C11/12, G11C11/14 take precedence
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 11/4026 using bipolar transistors
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/0821 Collector regions of bipolar transistors
• CPC Class Codes: H01L 29/1004 Base region of bipolar transistors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/772 : Field effect transistors
• CPC Class Codes: H01L 29/7841 : with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7855 : with at least two independent gates
• CPC Class Codes: H01L 29/7881 : Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 12/20 : DRAM devices comprising floating-body transistors, e.g. floating-body cells

Abstract

Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Claims

1. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells each include;

a first bipolar device having a first floating base region, a first collector, and a first emitter, and

a second bipolar device having a second floating base region, a second collector, and a second emitter,

wherein said first floating base region is common to said second floating base region,

wherein said first collector is common to said second collector,

wherein a state of said memory cell is maintained through a back-bias applied to said first and second collectors,

wherein said first and second collectors are commonly connected to at least two of said memory cells; and

a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors.

2. The semiconductor memory array of claim 1, wherein said first and second floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said first and second collectors and said region have said second conductivity type.

3. The semiconductor memory array of claim 1, wherein said back-bias applied to said first and second collectors is a constant voltage bias.

4. The semiconductor memory array of claim 1, wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

5. The semiconductor memory array of claim 1, wherein said semiconductor memory cell further comprises a gate region above said first and second floating base regions.

6. The semiconductor memory array of claim 1, wherein a maximum potential that can be stored in said first and second floating base regions is increased by said applying back bias to said semiconductor memory array, resulting in a relatively larger memory window.

7. The semiconductor memory array of claim 1, comprising fin structures extending from a substrate.

8. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each said semiconductor memory cell includes;

a first bipolar device having a first floating base region, a first collector, and a first emitter, and

a second bipolar device having a second floating base region, a second collector, and a second emitter,

wherein said first floating base region is common to said second floating base region,

wherein said first collector is common to said second collector,

wherein application of back-bias to said collector results in at least two stable floating base region charge levels,

wherein said first and second collectors are commonly connected to at least two of said memory cells; and

a region extending from and electrically connected to said first and second collectors, wherein said region has a conductivity type selected from a p-type conductivity type and an n-type conductivity type that is the same as a conductivity type of said first and second collectors.

9. The semiconductor memory array of claim 8, wherein said first and second floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said first and second emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said first and second collectors and said region have said second conductivity type.

10. The semiconductor memory array of claim 8, wherein said back-bias applied to said first and second collectors is a constant voltage bias.

11. The semiconductor memory array of claim 8, wherein said back-bias applied to said first and second collectors is a periodic pulse of voltage.

12. The semiconductor memory array of claim 8, wherein said semiconductor memory cell further comprises a gate region above said floating base regions.

13. The semiconductor memory array of claim 8, wherein a maximum potential that can be stored in said floating base regions is increased by said applying back bias to the cell, resulting in a relatively larger memory window.

14. The semiconductor memory array of claim 8, comprising fin structures extending from a substrate.

15. A semiconductor memory array comprising:

a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein each of said plurality of semiconductor memory cells includes;

a first bipolar device having a first floating base region, a first collector, and a first emitter; and

a second bipolar device having a second floating base region, a second collector, and a second emitter;

wherein said first floating base region is common to said second floating base region;

wherein said first collector is common to said second collector;

wherein states of said memory cells are maintained upon repeated read operations; and

a region having a conductivity type the same as a conductivity type of said first and second collectors, said region being electrically connected to said first and second collectors.

16. The semiconductor memory array of claim 15, wherein at least one of said first bipolar device or said second bipolar device maintains the state of said memory cell, and

wherein said first and second collectors are commonly connected to at least two of said memory cells.

17. The semiconductor memory array of claim 15, wherein said floating base regions have a first conductivity type selected from a p-type conductivity type and an n-type conductivity type;

each said emitters have a second conductivity type selected from said p-type and n-type conductivity types, said second conductivity type being different from said first conductivity type; and

said collectors and said region have said second conductivity type.

18. The semiconductor memory array of claim 15, wherein back-bias is applied to said first and second collectors via a voltage bias applied as a constant voltage bias, a periodic pulse of voltage, or a serial combination of constant voltage bias and periodic pulse of voltage.

19. The semiconductor memory array of claim 15, wherein a maximum potential that can be stored in said floating base regions is increased by applying back bias to the cell, resulting in a relatively larger memory window.

20. The semiconductor memory array of claim 15, comprising a fin structure extending from a substrate.