Method of forming staircase structures for three-dimensional memory device double-sided routing

• US 10,453,860 B1
• Filed: 09/22/2018
• Issued: 10/22/2019
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Original Assignee: Yangtze Memory Technologies Co., Ltd. (Yangtze River Storage Technology Holdings Co. , Ltd.)
• Inventors: Xiao, Li Hong
• Primary Examiner(s): Seven, Evren
• Application Number:
  US16/138,992
• Time in Patent Office: 395 Days
• Field of Search: None
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Embodiments of methods of forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. Dielectric/sacrificial layer pairs are formed on the first dielectric layer and filling in the recess. A second photoresist layer is formed on the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer is formed on the first dielectric layer and covering the patterned dielectric/sacrificial layer pairs. A memory stack including conductor/dielectric layer pairs is formed by replacing, with conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs and the dielectric/sacrificial layer pairs in the recess.

Claims

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming a first dielectric layer on a substrate and a first photoresist layer on the first dielectric layer;

patterning a recess through the first dielectric layer to the substrate by a plurality cycles of trimming the first photoresist layer and etching the first dielectric layer;

forming a plurality of dielectric/sacrificial layer pairs on a top surface of the first dielectric layer and filling in the recess;

forming a second photoresist layer on a top surface of the plurality of dielectric/sacrificial layer pairs;

patterning the plurality of dielectric/sacrificial layer pairs on the top surface of the first dielectric layer by a plurality cycles of trimming the second photoresist layer and etching the plurality of dielectric/sacrificial layer pairs;

forming a second dielectric layer on the top surface of the first dielectric layer and covering the patterned plurality of dielectric/sacrificial layer pairs; and

forming a memory stack on the substrate comprising a plurality of conductor/dielectric layer pairs by replacing, with a plurality of conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs on the top surface of the first dielectric layer and the dielectric/sacrificial layer pairs in the recess.

2. The method of claim 1, wherein forming the first dielectric layer comprises depositing a silicon oxide film.

3. The method of claim 1, wherein patterning the recess comprises:

patterning the first photoresist layer to expose a portion of the first dielectric layer;

etching the exposed portion of the first dielectric layer using the patterned first photoresist layer as an etch mask;

trimming the first photoresist layer to enlarge the exposed portion of the first dielectric layer;

etching the enlarged exposed portion of the first dielectric layer using the trimmed first photoresist layer as another etch mask to form a step structure at an edge of the recess; and

repeating the cycle of trimming and etching until the etching reaches the substrate and resulting in a plurality of step structures at the edge of the recess.

4. The method of claim 3, wherein in each cycle of trimming and etching, an amount of the trimmed first photoresist layer is the same.

5. The method of claim 3, wherein forming the plurality of dielectric/sacrificial layer pairs comprises:

alternatingly depositing dielectric layers and sacrificial layers, wherein a thickness of each of the dielectric/sacrificial layer pairs is the same as a depth of each of the step structures at the edge of the recess; and

planarizing the deposited dielectric layers and sacrificial layers.

6. The method of claim 5, wherein a number of the dielectric/sacrificial layer pairs on the top surface of the first dielectric layer after planarizing is the same as a number of the dielectric/sacrificial layer pairs in the recess.

7. The method of claim 4, wherein patterning the plurality of dielectric/sacrificial layer pairs comprises:

patterning the second photoresist layer to expose a portion of a first one of the dielectric/sacrificial layer pairs;

etching the exposed portion of the first dielectric/sacrificial layer pair using the patterned second photoresist layer as an etch mask to expose a portion of a second one of the dielectric/sacrificial layer pairs;

trimming the second photoresist layer to expose another portion of the first dielectric/sacrificial layer pair;

etching the exposed portions of the first and second dielectric/sacrificial layer pairs using the trimmed second photoresist layer as another etch mask to form a step structure at an edge of the dielectric/sacrificial layer pairs; and

repeating the cycle of trimming and etching until the etching reaches the top surface of the first dielectric layer and results in a plurality of step structures at the edge of the dielectric/sacrificial layer pairs.

8. The method of claim 7, wherein in each cycle of trimming and etching, an amount of the trimmed second photoresist layer is the same.

9. The method of claim 8, wherein forming the second dielectric layer comprises:

depositing a silicon oxide film; and

planarizing the silicon oxide film.

10. The method of claim 1, wherein forming the memory stack comprises:

etching a plurality of openings through the patterned plurality of dielectric/sacrificial layer pairs;

etching the sacrificial layers in the patterned plurality of dielectric/sacrificial layer pairs through the plurality of openings; and

depositing the conductor layers in the plurality of conductor/dielectric layer pairs through the plurality of openings.

11. A method for forming staircase structures of a three-dimensional (3D) memory device, comprising:

forming a dielectric layer on a substrate and a photoresist layer on the dielectric layer;

patterning a recess through the dielectric layer to the substrate by a plurality cycles of trimming the photoresist layer and etching the dielectric layer, such that a top aperture of the patterned recess is larger than a bottom aperture of the patterned recess, and a first plurality of step structures and a second plurality of step structures are formed at opposite edges of the patterned recess, respectively; and

forming a plurality of dielectric/sacrificial layer pairs filling in the patterned recess, such that a first staircase structure and a second staircase structure are formed at opposite edges of the plurality of dielectric/sacrificial layer pairs, respectively.

12. The method of claim 11, wherein the aperture of the patterned recess incrementally decreases from top to bottom.

13. The method of claim 11, wherein patterning the recess comprises:

patterning the photoresist layer to expose a portion of the dielectric layer;

etching the exposed portion of the dielectric layer using the patterned photoresist layer as an etch mask;

trimming the photoresist layer to enlarge the exposed portion of the dielectric layer;

etching the enlarged exposed portion of the dielectric layer using the trimmed photoresist layer as another etch mask; and

repeating the cycle of trimming and etching until the etching reaches the substrate.

14. A method for forming staircase structures of a three-dimensional (3D) memory device, comprising:

forming a dielectric layer on a substrate and a photoresist layer on the dielectric layer;

patterning a recess through the dielectric layer to the substrate by a plurality cycles of trimming the first photoresist layer and etching the dielectric layer;

forming a plurality of lower dielectric/sacrificial layer pairs filling in the recess, such that a top surface of the lower dielectric/sacrificial layer pairs flushes with a top surface of the dielectric layer, and a first staircase structure and a second staircase structure are formed at opposite edges of the lower dielectric/sacrificial layer pairs, respectively;

forming a plurality of upper dielectric/sacrificial layer pairs on the top surfaces of the dielectric layer and the lower dielectric/sacrificial layer pairs;

forming a second photoresist layer on a top surface of the upper dielectric/sacrificial layer pairs; and

patterning the upper dielectric/sacrificial layer pairs by a plurality cycles of trimming the second photoresist layer and etching the upper dielectric/sacrificial layer pairs, such that a third staircase structure and a fourth staircase structure are formed at opposite edges of the upper dielectric/sacrificial layer pairs, respectively.

15. The method of claim 14, wherein forming the dielectric layer comprises depositing a silicon oxide film.

16. The method of claim 14, wherein patterning the recess comprises:

patterning the first photoresist layer to expose a portion of the dielectric layer;

etching the exposed portion of the dielectric layer using the patterned first photoresist layer as an etch mask;

trimming the first photoresist layer to enlarge the exposed portion of the dielectric layer;

etching the enlarged exposed portion of the dielectric layer using the trimmed first photoresist layer as another etch mask to form a first step structure and a second step structure at opposite edges of the recess, respectively; and

repeating the cycle of trimming and etching until the etching reaches the substrate and resulting in a first plurality of step structures and a second plurality of step structures at the opposite edges of the recess, respectively.

17. The method of claim 16, wherein in each cycle of trimming and etching, an amount of the trimmed first photoresist layer is the same.

18. The method of claim 14, wherein forming the plurality of upper dielectric/sacrificial layer pairs comprises planarizing the upper dielectric/sacrificial layer pairs, such that a number of the upper dielectric/sacrificial layer pairs is the same as a number of the lower dielectric/sacrificial layer pairs.

19. The method of claim 14, wherein patterning the plurality of upper dielectric/sacrificial layer pairs comprises:

patterning the second photoresist layer to expose a portion of a first one of the upper dielectric/sacrificial layer pairs;

etching the exposed portion of the first upper dielectric/sacrificial layer pair using the patterned second photoresist layer as an etch mask to expose a portion of a second one of the upper dielectric/sacrificial layer pairs;

trimming the second photoresist layer to expose another portion of the first upper dielectric/sacrificial layer pair;

etching the exposed portions of the first and second upper dielectric/sacrificial layer pairs using the trimmed second photoresist layer as another etch mask; and

repeating the cycle of trimming and etching until the etching reaches the top surface of the first dielectric layer.

20. The method of claim 19, wherein in each cycle of trimming and etching, an amount of the trimmed second photoresist layer is the same.