Method for manufacturing thin film transistor and display panel

• US 10,453,876 B2
• Filed: 04/20/2015
• Issued: 10/22/2019
• Est. Priority Date: 04/20/2015
• Status: Active Grant

• Current Assignee: Sakai Display Products Corporation (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sakai Display Products Corporation (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nodera, Nobutake, Ishida, Shigeru, Takakura, Ryohei, Matsushima, Yoshiaki, Matsumoto, Takao
• Primary Examiner(s): Ward, Eric A.
• Application Number:
  US15/567,518
• Publication Number:
  US 20180122839A1
• Time in Patent Office: 1,646 Days
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02678 Beam shaping, e.g. using a mask
• CPC Class Codes: H01L 2223/5442 comprising non digital, non alphanumeric information, e.g. symbols
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape. Thereafter, when a metal layer for the source electrode and the drain electrode is formed, the shape of the cleared portion, which is a recessed portion, is followed, thereby forming a depression in the metal layer. Consequently, the depression is used as an alignment mark, and the source electrode and the drain electrode are formed at appropriate positions on the upper side of the channel region.

Claims

1. A method for manufacturing a thin film transistor, comprising the processes of:

forming a gate electrode on a surface of a substrate;

forming an insulation film on the surface of the substrate on which the gate electrode is formed;

forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed;

annealing a channel region in the first amorphous silicon layer by irradiating the channel region with an energy beam to be changed to a polysilicon layer;

during the annealing process, forming a removed part for an alignment mark in the first amorphous silicon layer with the energy beam;

forming a second amorphous silicon layer so as to cover the polysilicon layer;

forming an n+ silicon layer on the second amorphous silicon layer;

forming a required pattern at the n+ silicon layer;

etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer;

forming a metal layer on the surface of the substrate after the etching process; and

forming source electrode and drain electrode by patterning the metal layer based on a position of a concave formed in the metal layer during forming the metal layer due to a presence of the removed part, wherein

the annealing process and the removed part forming process are simultaneously performed using a halftone mask having a plurality of transmissive parts with different transmittances from each other.

2. A method for manufacturing a thin film transistor, comprising the processes of:

forming a gate electrode on a surface of a substrate;

forming an insulation film on the surface of the substrate on which the gate electrode is formed;

forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed;

annealing a channel region in the first amorphous silicon layer by irradiating the channel region with an energy beam to be changed to a polysilicon layer;

during the annealing process, forming a removed part for an alignment mark in the first amorphous silicon layer with the energy beam;

forming a second amorphous silicon layer so as to cover the polysilicon layer;

forming an n+ silicon layer on the second amorphous silicon layer;

forming a required pattern at the n+ silicon layer;

etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer;

forming a metal layer on the surface of the substrate after the etching process; and

forming source electrode and drain electrode by patterning the metal layer based on a position of a concave formed in the metal layer during forming the metal layer due to a presence of the removed part, wherein the concave is formed in the vicinity of the channel region, above a gate bus line connected with the gate electrode.

3. A display panel provided with a thin film transistor and an alignment mark used in a patterning of a source electrode and a drain electrode of the thin film transistor, wherein

the thin film transistor includes:

a gate electrode formed on a surface of a substrate;

an insulation film formed on the substrate and on the gate electrode;

a polysilicon layer formed at a channel region above the gate electrode in a first amorphous silicon layer formed on the insulation film by irradiating the channel region with an energy beam;

an inside portion of the thin film transistor in the first amorphous silicon layer, which is formed above the gate electrode by etching the first amorphous silicon layer;

a second amorphous silicon layer formed on the inside portion of the thin film transistor in the first amorphous silicon layer and on the polysilicon layer;

an n+ silicon layer formed on the second amorphous silicon layer; and

the source electrode and the drain electrode formed by patterning a metal layer formed on the surface of the substrate after forming of the n+ silicon layer, and

the display panel includes;

a removed part formed for an alignment mark in the first amorphous silicon layer by irradiating with the energy beam; and

a concave formed as the alignment mark in the metal layer due to a presence of the removed part, the metal layer being formed on a portion surrounding the removed part of the first amorphous silicon layer and on the removed part and, wherein the concave is formed in the vicinity of the gate electrode, above a gate bus line connected with the gate electrode.

4. The display panel according to claim 3, wherein the inside portion of the thin film transistor in the first amorphous silicon layer is formed around the polysilicon layer and has a thickness approximately equal to that of the polysilicon layer.