Semiconductor apparatus and equipment having laminated layers

• US 10,453,888 B2
• Filed: 03/22/2018
• Issued: 10/22/2019
• Est. Priority Date: 03/30/2017
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Kobayashi, Masahiro
• Primary Examiner(s): Coleman, William
• Application Number:
  US15/928,997
• Publication Number:
  US 20180286910A1
• Time in Patent Office: 579 Days
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14636 Interconnect structures

Abstract

In a semiconductor apparatus including: a semiconductor substrate in which a plurality of semiconductor elements are provided; a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided; a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer; a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer; a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, widths of a plurality of through electrodes are different from each other.

Claims

1. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer in which a plurality of semiconductor elements are provided and which is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the first wiring structure and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the second semiconductor layer is arranged between the first wiring structure and the third wiring structure,

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the second wiring structure includes a second wiring;

the third wiring structure includes a third wiring;

a through electrode that passes through the first semiconductor layer and reaches the first wiring; and

a through electrode that passes through the second semiconductor layer and reaches the third wiring are further included, and

a width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is different from a width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring.

2. The semiconductor apparatus according to claim 1, wherein:

the third wiring is electrically connected to the first wiring;

the third wiring structure includes a fourth wiring that is electrically connected to the second wiring; and

the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is narrower than the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring.

3. The semiconductor apparatus according to claim 1, wherein:

the third wiring is electrically connected to the first wiring;

the third wiring structure includes a fourth wiring that is electrically connected to the second wiring; and

the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is wider than the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring.

4. The semiconductor apparatus according to claim 1, wherein the through electrode reaching the first wiring connects a pixel circuit unit that is constituted by the first wiring structure and the first semiconductor layer and a column circuit unit that is constituted by the third wiring structure and the semiconductor substrate.

5. The semiconductor apparatus according to claim 1, wherein the through electrode reaching the first wiring is overlapped on the through electrode reaching the third wiring.

6. The semiconductor apparatus according to claim 1, wherein the second semiconductor layer and the second wiring structure constitute a DRAM cell array.

7. The semiconductor apparatus according to claim 1, wherein a thickness of the second semiconductor layer is thicker than a thickness of the first semiconductor layer and thinner than a thickness of the semiconductor substrate.

8. The semiconductor apparatus according to claim 1, wherein a thickness of the semiconductor substrate is greater than twice of a distance from the semiconductor substrate to a surface of the first semiconductor layer, which is opposite to the first main surface, and smaller than 20 times of the distance.

9. Equipment comprising:

the semiconductor apparatus according to claim 1, wherein at least one of an optical system that forms an image in the semiconductor apparatus, a control apparatus that controls the semiconductor apparatus, a processing apparatus that processes a signal output from the semiconductor apparatus, a display apparatus that displays information obtained by the semiconductor apparatus, and a memory apparatus that stores information obtained by the semiconductor apparatus is further included.

10. The semiconductor apparatus according to claim 1, wherein

the third wiring structure includes a fourth wiring, and the semiconductor apparatus further comprises a through electrode that passes through the second semiconductor layer and reaches the fourth wiring.

11. The semiconductor apparatus according to claim 1, further comprising a through electrode that passes through the second semiconductor layer and reaches the second wiring,

wherein the second wiring structure is arranged between the second semiconductor layer and the third wiring structure, and the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is different from a width, at a position coplanar with the second main surface, of the through electrode reaching the second wiring.

12. The semiconductor apparatus according to claim 10, wherein the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is narrower than a width, at a position coplanar with the second main surface, of a the through electrode reaching the fourth wiring.

13. The semiconductor apparatus according to claim 10, wherein the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring is wider than a width, at a position coplanar with the second main surface, of the through electrode reaching the fourth wiring.

14. The semiconductor apparatus according to claim 10, wherein the third wiring structure includes a fifth wiring that is connected to a pad included in the first wiring structure, a through electrode that passes through the second semiconductor layer and reaches the fifth wiring is further included, and a width, at a position coplanar with the second main surface, of the through electrode reaching the fifth wiring is wider than the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring.

15. The semiconductor apparatus according to claim 10, wherein:

the first semiconductor layer includes a pixel region in which the plurality of photoelectric conversion elements are arrayed; and

the through electrode reaching the fourth wiring is arranged between the pixel region and the semiconductor substrate.

16. The semiconductor apparatus according to claim 10, wherein the third wiring structure includes a fifth wiring that is connected to a pad included in the first wiring structure, a through electrode that passes through the second semiconductor layer and reaches the fifth wiring is further included, and a width, at a position coplanar with the second main surface, of the through electrode reaching the fifth wiring is wider than a width, at a position coplanar with the second main surface, of a through electrode reaching the fourth wiring.

17. The semiconductor apparatus according to claim 11, further comprising:

a fourth wiring structure arranged between the second semiconductor layer and the first wiring structure, the fourth wiring structure including a fourth wiring; and

a through electrode that passes through the first semiconductor layer and reaches the fourth wiring,

wherein a width, at a position coplanar with the first main surface, of the through electrode reaching the fourth wiring is different from the width, at a position coplanar with the second main surface, of the through electrode reaching the second wiring.

18. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer in which a plurality of semiconductor elements are provided and which is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the first wiring structure and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the second semiconductor layer is arranged between the first wiring structure and the third wiring structure,

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring and a second wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the third wiring structure includes a third wiring that is electrically connected to the first wiring and a fourth wiring that is electrically connected to the second wiring;

a through electrode that passes through the first semiconductor layer and reaches the first wiring; and

a through electrode that passes through the first semiconductor layer and reaches the second wiring are included, and

a width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is different from a width, at a position coplanar with the first main surface, of the through electrode reaching the second wiring.

19. The semiconductor apparatus according to claim 18, wherein the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is narrower than the width, at a position coplanar with the first main surface, of the through electrode reaching the second wiring.

20. The semiconductor apparatus according to claim 18, wherein the width, at a position coplanar with the first main surface, of the through electrode reaching the first wiring is wider than the width, at a position coplanar with the first main surface, of the through electrode reaching the second wiring.

21. The semiconductor apparatus according to claim 18, wherein one of the through electrode reaching the first wiring and the through electrode reaching the second wiring is a first through electrode, the other of the through electrode reaching the first wiring and the through electrode reaching the second wiring is a second through electrode,

a width, at a position coplanar with the first main surface, of the first through electrode is wider than a width, at a position coplanar with the first main surface, of the second through electrode, and

a distance between the first through electrode and an outer edge of the first semiconductor layer is shorter than a distance between the second through electrode and the outer edge of the first semiconductor layer.

22. The semiconductor apparatus according to claim 18, further comprising a through electrode that passes through the first semiconductor layer and reaches a fifth wiring included in the second wiring structure, wherein the second wiring structure is arranged between the second semiconductor layer and the first wiring structure.

23. A semiconductor apparatus comprising:

a semiconductor substrate in which a plurality of semiconductor elements are provided;

a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided;

a second semiconductor layer in which a plurality of semiconductor elements are provided and which is arranged between the semiconductor substrate and the first semiconductor layer;

a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer;

a second wiring structure that is arranged between the first wiring structure and the semiconductor substrate; and

a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, wherein;

the second semiconductor layer is arranged between the first wiring structure and the third wiring structure,

the first semiconductor layer includes a first main surface on a side of the first wiring structure;

the first wiring structure includes a first wiring;

the second semiconductor layer includes a second main surface on a side of the second wiring structure;

the second wiring structure includes a second wiring;

the third wiring structure includes a third wiring and a fourth wiring;

a through electrode that passes through the second semiconductor layer and reaches the third wiring; and

a through electrode that passes through the second semiconductor layer and reaches the fourth wiring, and

a width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring is different from a width, at a position coplanar with the second main surface, of the through electrode reaching the fourth wiring.

24. The semiconductor apparatus according to claim 23, wherein the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring is wider than the width, at a position coplanar with the second main surface, of the through electrode reaching the fourth wiring.

25. The semiconductor apparatus according to claim 23, wherein the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring is narrower than the width, at a position coplanar with the second main surface, of the through electrode reaching the fourth wiring.

26. The semiconductor apparatus according to claim 23, wherein one of the through electrode reaching the first wiring and the through electrode reaching the second wiring is a first through electrode, the other of the through electrode reaching the first wiring and the through electrode reaching the second wiring is a second through electrode,

a width, at a position coplanar with the first main surface, of the first through electrode is wider than a width, at a position coplanar with the first main surface, of the second through electrode, and

a distance between the first through electrode and an outer edge of the second semiconductor layer is shorter than a distance between a through electrode and the outer edge of the second semiconductor layer.

27. Equipment that includes a machine apparatus, further comprising:

the semiconductor apparatus according to claim 23; and

a processing apparatus that performs, on a basis of information obtained by the semiconductor apparatus, processing for operating the machine apparatus.

28. The semiconductor apparatus according to claim 23, further comprising a through electrode that passes through the second semiconductor layer and reaches the second wiring, wherein the second wiring structure is arranged between the second semiconductor layer and the third wiring structure.

29. The semiconductor apparatus according to claim 23, further comprising:

a through electrode that passes through the second semiconductor layer and reaches the second wiring included in the second wiring structure, and

a through electrode that passes through the second semiconductor layer and reaches a fifth wiring included in the second wiring structure,

wherein a width, at a position coplanar with the second main surface, of the through electrode reaching the second wiring is different from the width, at a position coplanar with the second main surface, of the through electrode reaching the fifth wiring.

30. The semiconductor apparatus according to claim 29, further comprising a through electrode that passes through the second semiconductor layer and reaches the second wiring included in the second wiring structure,

wherein a width, at a position coplanar with the second main surface, of the through electrode reaching the second wiring is different from the width, at a position coplanar with the second main surface, of the through electrode reaching the third wiring.