Low substrate leakage Zener diode with modulated buried junction

• US 10,453,914 B2
• Filed: 01/07/2019
• Issued: 10/22/2019
• Est. Priority Date: 10/31/2017
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Cai, Jun, Hu, Binghua
• Primary Examiner(s): Mandala, Victor A
• Application Number:
  US16/241,076
• Publication Number:
  US 20190157382A1
• Time in Patent Office: 288 Days
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/66106 Zener diodes
• CPC Class Codes: H01L 29/866 Zener diodes
• CPC Class Codes: H01L 29/868 PIN diodes

Abstract

In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Claims

1. An apparatus, comprising:

a semiconductor layer doped with a first-type dopant;

a first region doped with the first-type dopant and formed in the semiconductor layer;

a second region doped with the first-type dopant and formed in the semiconductor layer;

a third region doped with a second-type dopant and formed in the semiconductor layer, the second-type dopant is opposite the first-type dopant, the first, second, and third regions are non-overlapping, and the third region is positioned between the first region and the second region; and

a plurality of Zener implant regions buried in the semiconductor layer and the third region, each of the plurality of Zener implant regions configured to generate a different pinch-off region.

2. The apparatus of claim 1, wherein the third region and the semiconductor layer are configured to form a plurality of avalanche regions, wherein each of the plurality of Zener implant regions is positioned between a pair of the plurality of avalanche regions.

3. The apparatus of claim 2, wherein at least one of the pinch-off regions is derived from the pair of the plurality of avalanche regions.

4. The apparatus of claim 1, wherein each of the plurality of Zener implant regions comprises a first doped well and a second doped well, wherein the first doped well is implanted in a portion of the third region and the second doped well is implanted in a portion of the semiconductor layer.

5. The apparatus of claim 4, wherein the first doped well forms an n-side of each of the plurality of Zener implant regions and the second doped well forms a p-side of each of the plurality of the Zener implant regions.

6. The apparatus of claim 1, further comprising a first isolation layer and a second isolation layer, wherein the first isolation layer extends from the third region to the first region, and the second isolation layer extends from the third region to the second region.

7. The apparatus of claim 1, wherein the first-type dopant is a group III element and the second-type dopant is a group V element.

8. The apparatus of claim 1, wherein at least one of the Zener implant regions is configured to form multiple modulation regions that generate a pinch-off region.

9. An apparatus, comprising:

a semiconductor layer doped with a first-type dopant;

a first region doped with the first-type dopant and formed at a first position in the semiconductor layer;

a second region doped with the first-type dopant and formed at a second position in the semiconductor layer; and

multiple, non-overlapping, highly-doped regions buried in the semiconductor layer and in a lightly-doped region,

wherein the apparatus comprises a buried Zener diode.

10. The apparatus of claim 9, wherein the lightly-doped region and the semiconductor layer are configured to form a plurality of avalanche regions, wherein each of the highly-doped regions is positioned between a pair of the plurality of avalanche regions.

11. The apparatus of claim 10, wherein each of the highly-doped regions is configured to generate a pinch-off region derived from the pair of the plurality of avalanche regions.

12. The apparatus of claim 9, wherein each of the highly-doped regions comprises a first doped well and a second doped well, wherein the first doped well is implanted in a portion of the lightly-doped region and the second doped well is implanted in a portion of the semiconductor layer.

13. The apparatus of claim 12, wherein at least one of the first doped wells forms an n-side of the highly-doped region and wherein at least one of the second doped wells forms a p-side of the highly-doped region.

14. The apparatus of claim 9, wherein at least one of the highly-doped regions is configured to form multiple modulation regions that generate a pinch-off region due to an increased electric field from the multiple modulation regions.

15. The apparatus of claim 14, wherein the at least one of the highly-doped regions is configured to form the multiple modulations regions in response to the apparatus receiving a reverse-bias voltage.