Conformal doping for punch through stopper in fin field effect transistor devices

• US 10,453,922 B2
• Filed: 11/22/2016
• Issued: 10/22/2019
• Est. Priority Date: 10/26/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bu, Huiming, Kanakasabapathy, Sivananda K., Lie, Fee Li, Yamashita, Tenko
• Primary Examiner(s): Vu, Hung K
• Application Number:
  US15/358,661
• Publication Number:
  US 20170117365A1
• Time in Patent Office: 1,064 Days
• Field of Search: None
• CPC Class Codes: H01L 21/223 using diffusion into or out of a solid from or into a gaseous phase H01L21/221 - H01L21/222 take precedence; diffusion through an applied layer H01L21/225
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66803 with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants

Abstract

A method of forming a punch through stop region that includes forming isolation regions of a first dielectric material between adjacent fin structures and forming a spacer of a second dielectric material on sidewalls of the fin structure. The first dielectric material of the isolation region may be recessed with an etch process that is selective to the second dielectric material to expose a base sidewall portion of the fin structures. Gas phase doping may introduce a first conductivity type dopant to the base sidewall portion of the fin structure forming a punch through stop region underlying a channel region of the fin structures.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a spacer on sidewalls of fin structures, wherein dielectric isolation regions are adjacent to base portions of the fin structures;

exposing a portion of the fin structures underlying the spacer;

doping the exposed portion of the fin structures underlying the spacer with a dopant having a first conductivity type to form a punch through stop region;

depositing a dielectric material in direct contact with bottom sidewalls of the spacer and in direct contact with the punch through stop region;

removing the spacer after depositing the dielectric material; and

forming source and drain regions on source and drain region portions of the fin structures, the source and drain regions doped with a second conductivity type dopant.

2. The method of claim 1, wherein the spacer includes a nitride.

3. The method of claim 1, further comprising a hard mask present on an upper surface of the fin structures.

4. The method of claim 1, wherein said forming the spacer includes depositing a conformal dielectric layer on the fin structures, and anisotropically etching the conformal dielectric layer to remove horizontal portions that are overlying the dielectric isolation regions.

5. The method of claim 1, wherein said exposing said portion of the fin structures comprises recessing the dielectric isolation regions to expose a portion of the fin structures underlying the spacer by an etch process that is selective to the spacer.

6. The method of claim 5, wherein the etch process that is selective to the spacer is isotropic.

7. The method of claim 1, wherein said doping the exposed portion of the fin structures underlying the spacer comprises gas phase doping.

8. The method of claim 1, wherein said doping the exposed portion of the fin structures underlying the spacer to form the punch through stop region further comprises an activation anneal.

9. The method of claim 1, further comprising forming a gate structure on a channel region of the fin structures.

10. A method of forming a semiconductor device, the method comprising:

forming a spacer on sidewalls of fin structures, wherein dielectric isolation regions are adjacent to base portions of the fin structures;

exposing a portion of the fin structures underlying the spacer;

doping the exposed portion of the fin structures underlying the spacer with a dopant having a first conductivity type to form a punch through stop region, a lower surface of the punch through stop region being substantially coplanar with an upper surface of the dielectric isolation regions;

depositing a dielectric material in direct contact with bottom sidewalls of the spacer and in direct contact with the punch through stop region;

removing the spacer after depositing the dielectric material; and

forming source and drain regions on the source and drain region portions of the fin structure, the source and drain regions doped with a second conductivity type dopant.

11. The method of claim 10, wherein exposing said portion of the fin structures comprises recessing the dielectric isolation regions to expose a portion of the fin structures underlying the spacer by an etch process that is selective to the spacer.

12. The method of claim 11, wherein said recessing the dielectric isolation regions comprises an etch process that is selective to the spacer.

13. The method of claim 12, wherein the etch process that is selective to the spacer is isotropic.

14. The method of claim 10, further comprising a hard mask present on an upper surface of the fin structures.

15. The method of claim 10, wherein said forming the spacer includes depositing a conformal dielectric layer on the fin structures;

and anisotropically etching the conformal dielectric layer to remove horizontal portions that are overlying the dielectric isolation regions.

16. The method of claim 10, wherein said forming the punch through stop region further comprises an activation anneal.