Semiconductor device having termination trench

• US 10,453,931 B2
• Filed: 11/09/2018
• Issued: 10/22/2019
• Est. Priority Date: 08/28/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Blank, Oliver, Hirler, Franz, Siemieniec, Ralf, Yip, Li Juin
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US16/185,727
• Publication Number:
  US 20190097005A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.

Claims

1. A semiconductor device comprising:

a semiconductor substrate structure comprising a cell region and an edge termination region;

a plurality of cell trenches within the cell region extending from a surface of the semiconductor substrate structure into the semiconductor substrate structure, the plurality of cell trenches each comprising an insulation layer; and

a plurality of edge termination trenches within the edge termination region extending from a surface of the semiconductor substrate structure into the semiconductor substrate structure, the plurality of edge termination trenches each comprising an insulation layer,

wherein the edge termination trenches and the cell trenches comprise a same type of needle shaped trenches, and

wherein the semiconductor substrate structure comprises a doping concentration that increases with a distance from the surface of the semiconductor substrate structure.

2. The semiconductor device of claim 1, wherein the edge termination region surrounds the cell region in a plan view.

3. The semiconductor device of claim 1, wherein an outermost row of cell trenches has the same insulation layer thickness as an innermost row of edge termination trenches.

4. The semiconductor device of claim 1, wherein the insulation layer of an innermost row of edge termination trenches is thinner than the insulation layer of an outermost row of edge termination trenches.

5. The semiconductor device of claim 1, wherein the insulation layer of an intermediate row of edge termination trenches is thicker than the insulation layer of an innermost row of edge termination trenches, and thinner than the insulation layer of an outermost row of edge termination trenches.

6. The semiconductor device of claim 1, wherein the insulation layers of an outermost row of edge termination trenches are merged.

7. The semiconductor device of claim 1, wherein the insulation layer of the plurality of cell trenches and the insulation layer of the plurality of edge termination trenches comprise a round layout in a plan view.

8. The semiconductor device of claim 1, wherein the plurality of cell trenches and the plurality of edge termination trenches comprise a field plate insulated from the semiconductor substrate structure by the respective insulating layers.

9. The semiconductor device of claim 8, wherein an area of the field plate associated with one of the plurality of cell trenches and an area of the field plate associated with one of the plurality of edge termination trenches are same in a plan view.

10. The semiconductor device of claim 1, wherein the insulation layer of at least one of the plurality of cell trenches is thinner than the insulation layer of at least one of the plurality of edge termination trenches.

11. The semiconductor device according to claim 1, the plurality of cell trenches are active needle-shaped cell trenches, each of the active needle-shaped cell trenches comprising a gate structure for controlling an adjacent channel of a field effect transistor structure.

12. The semiconductor device according to claim 1, wherein each of the plurality of cell trenches comprises a maximal lateral extension in one direction of less than 2 times a minimal lateral extension in another direction.

13. The semiconductor device according to claim 1, wherein a lateral distance between an outermost edge termination trench and an active cell trench closest to the outermost edge termination trench is larger than an extension of the outermost edge termination trench from the surface of the semiconductor substrate structure into the semiconductor substrate structure.

14. The semiconductor device according to claim 1, wherein each of the plurality of edge termination trenches comprises one of a rectangular layout, a square layout, a round layout, a curved layout, a hexagonal layout or an octagonal layout.

15. The semiconductor device according to claim 1, wherein edge termination trenches of the plurality of edge termination trenches extend mainly in parallel to edges of the semiconductor substrate structure and comprise diagonals or curvatures at corner regions of the semiconductor substrate structure.

16. The semiconductor device according to claim 1, wherein an inner layout line of each edge termination trench has a diagonal straight with an angle between 35°

and 55°

to a neighboring straight, whereas the diagonal straight faces a corner of the cell region.

17. The semiconductor device according to claim 1, wherein an inner layout line of the edge termination trench which faces the cell region is designed in a way that a distance from each point of the inner layout line to a nearest point of an outline of a nearest cell trench deviates by less than 20% from an average distance between the inner layout line of the edge termination trench and the nearest point of the outline of the nearest cell trench.

18. The semiconductor device according to claim 1, wherein the edge termination region comprises an additional implantation relative to the cell region.

19. The semiconductor device according to claim 1, wherein the plurality of cell trenches is aligned in a rectangular, shifted or hexagonal grid.

20. The semiconductor device according to claim 1, wherein a field plate structure extends inside each trench of the plurality of cell trenches and the plurality of edge termination trenches and the field plate structures are insulated from the semiconductor substrate structure within the trenches by the respective insulation layers, and wherein the insulation layer within the plurality of cell trenches is thinner than the insulation layer within the plurality of edge termination trenches.