Vertical field effect transistor with strained channel region extension

• US 10,453,940 B1
• Filed: 06/26/2018
• Issued: 10/22/2019
• Est. Priority Date: 06/26/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mochizuki, Shogo, Lee, Choonghyun, Li, Juntao, Cheng, Kangguo
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US16/018,289
• Time in Patent Office: 483 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78684 having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys H01L29/7869 takes precedence

Abstract

According to one or more embodiments of the present invention, a method for forming a fin structure for a semiconductor device includes forming a fin. The method further includes recessing a first portion of the fin to form a recess in the fin. The method further includes forming a channel region in the first portion of the fin. The method further includes forming an extension region on a second portion of the fin, and wherein defects are collected within the extension regions from the channel region in the first portion of the fin.

Claims

1. A method for forming a fin structure for a semiconductor device, the method comprising:

forming a fin;

recessing a first portion of the fin to form a recess in the fin;

forming a channel region in the first portion of the fin;

forming an extension region on a second portion of the fin;

wherein the recess extends into the extension region;

wherein defects are collected within the extension region from the channel region in the first portion of the fin;

wherein an interface associated with the channel region, the fin and a spacer is free of defects.

2. The method of claim 1, strained silicon germanium is epitaxially grown in the recess.

3. The method of claim 1, further comprising forming a source/drain on the second portion of the fin.

4. The method of claim 3, wherein the source/drain is epitaxially grown on the second portion of the fin.

5. The method of claim 4, wherein dopants associated with the source/drain is used to form the extension region.

6. The method of claim 5, wherein an annealing process is used to drive dopants from the source/drain into the extension region.

7. The method of claim 1, the recess is formed using first etch to remove a first portion of the fin and a second etch to remove a second portion of the fin.

8. A method for forming a semiconductor device, the method comprising:

forming a first source/drain on a semiconductor substrate;

forming a first spacer on the first source/drain;

forming a fin on a portion of the first spacer;

recessing a first portion of the fin to form a recess in the fin;

forming a channel region in the first portion of the fin; and

forming a first extension region on a second portion of the fin;

wherein the recess extends into the first extension region on the second portion of the fin;

wherein defects are collected within the extension regions from the channel region in the first portion of the fin;

wherein an interface associated with the channel region, the fin and the first spacer is free of defects.

9. The method of claim 8 further comprising:

forming a second spacer on a third portion of the fin;

forming a second source/drain on the second spacer and the third portion of the fin; and

forming a second extension region on the third portion of the fin.

10. The method of claim 9, wherein dopants associated with the first source/drain are used to form the extension region on the second portion of the fin and dopants associated with the first source/drain are used to form the extension region on the third portion of the fin.

11. The method of claim 8, wherein an interface associated with the channel region, the fin and the second spacer is substantially free of defects.

12. The method of claim 8, wherein the recess extends into the second extension region on the third portion of the fin.

13. The method of claim 8, wherein strained silicon germanium is epitaxially grown in the recess.

14. The method of claim 8, wherein the recess is formed using a first etch to remove a first portion of the fin and a second etch to remove a second portion of the fin.