Semiconductor device including resonant tunneling diode structure having a superlattice

• US 10,453,945 B2
• Filed: 08/07/2017
• Issued: 10/22/2019
• Est. Priority Date: 08/08/2016
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Atomera Incorporated
• Inventors: Mears, Robert J., Takeuchi, Hideki, Hytha, Marek
• Primary Examiner(s): Abdelaziez, Yasser A
• Application Number:
  US15/670,231
• Publication Number:
  US 20180040724A1
• Time in Patent Office: 806 Days
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/157 Doping structures, e.g. doping superlattices, nipi superlattices delta doping in general H01L29/365
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/66007 Multistep manufacturing processes
• CPC Class Codes: H01L 29/6603 Diodes
• CPC Class Codes: H01L 29/66121 Multilayer diodes, e.g. PNPN diodes
• CPC Class Codes: H01L 29/66151 Tunnel diodes group 13/15 resonant tunneling diodes H01L29/66219
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/7376 Resonant tunnelling transistors
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7842 means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate variation of the composition of the channel H01L29/1054
• CPC Class Codes: H01L 29/8618 Diodes with bulk potential barrier, e.g. Camel diodes, Planar Doped Barrier diodes, Graded bandgap diodes
• CPC Class Codes: H01L 29/882 Resonant tunneling diodes, i.e. RTD, RTBD

Abstract

A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.

Claims

1. A semiconductor device comprising:

at least one double-barrier resonant tunneling diode (DBRTD) comprising;

a first doped semiconductor layer comprising silicon;

a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

an intrinsic semiconductor layer on the first barrier layer comprising at least one of silicon and germanium;

a second barrier layer on the intrinsic semiconductor layer; and

a second doped semiconductor layer on the second barrier layer comprising silicon.

2. The semiconductor device of claim 1 wherein the second barrier layer comprises a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained with a crystal lattice of adjacent base semiconductor portions.

3. The semiconductor device of claim 2 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer.

4. The semiconductor device of claim 1 wherein the second barrier layer comprises an oxide layer.

5. The semiconductor device of claim 4 wherein the second doped semiconductor layer comprises a polycrystalline semiconductor layer.

6. The semiconductor device of claim 1 wherein the first and second doped semiconductor layers have a same dopant conductivity type.

7. The semiconductor device of claim 1 wherein the first and second doped semiconductor layers have opposite dopant conductivity types.

8. The semiconductor device of claim 1 wherein the at least one DBRTD comprises a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE).

9. The semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen, and wherein the plurality of stacked base semiconductor monolayers each comprises silicon.

10. A semiconductor device comprising:

at least one double-barrier resonant tunneling diode (DBRTD) comprising

a first doped semiconductor layer;

a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

an intrinsic semiconductor layer on the first barrier layer;

a second barrier layer on the intrinsic semiconductor layer, the second barrier layer comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and

a second doped semiconductor layer on the second barrier layer.

11. The semiconductor device of claim 10 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the intrinsic layer comprises at least one of silicon and germanium.

12. The semiconductor device of claim 10 wherein the second doped semiconductor layer comprises a single crystal semiconductor layer.

13. The semiconductor device of claim 10 wherein the first and second doped semiconductor layers have a same dopant conductivity type.

14. The semiconductor device of claim 10 wherein the first and second doped semiconductor layers have opposite dopant conductivity types.

15. The semiconductor device of claim 10 wherein the at least one DBRTD comprises a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE).

16. A semiconductor device comprising:

at least one double-barrier resonant tunneling diode (DBRTD) comprising

a first doped semiconductor layer;

a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;

an intrinsic semiconductor layer on the first barrier layer;

a second barrier layer on the intrinsic semiconductor layer comprising an oxide layer; and

a second doped semiconductor layer on the second barrier layer.

17. The semiconductor device of claim 16 wherein the first and second doped semiconductor layers each comprises silicon, and wherein the intrinsic layer comprises at least one of silicon and germanium.

18. The semiconductor device of claim 16 wherein the second doped semiconductor layer comprises a polycrystalline semiconductor layer.

19. The semiconductor device of claim 16 wherein the first and second doped semiconductor layers have the same dopant conductivity type.

20. The semiconductor device of claim 16 wherein the first and second doped semiconductor layers have opposite dopant conductivity types.

21. The semiconductor device of claim 16 wherein the at least one DBRTD comprises a pair of DBRTDs connected in series to define a monostable-bistable transition logic element (MOBILE).

22. A semiconductor device comprising:

at least one double-barrier resonant tunneling diode (DBRTD) comprising;

a first doped semiconductor layer;

a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;

an intrinsic semiconductor layer on the first barrier layer;

a second barrier layer on the intrinsic semiconductor layer comprising an oxide; and

a second doped semiconductor layer on the second barrier layer.

23. The semiconductor device of claim 22 wherein the second doped semiconductor layer comprises a polycrystalline semiconductor layer.