Semiconductor device

• US 10,453,952 B2
• Filed: 09/08/2016
• Issued: 10/22/2019
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Industries Limited (Sumitomo Corporation)
• Inventors: Shiomi, Hiromu, Kitai, Hidenori, Tamaso, Hideto, Fukuda, Kenji
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US15/755,892
• Publication Number:
  US 20180315813A1
• Time in Patent Office: 1,139 Days
• CPC Class Codes: H01L 21/0465 using masks
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.

Claims

1. A semiconductor device having a surface outer circumferential portion, the semiconductor device comprising:

a first conductivity type thin film;

a second conductivity type thin film provided on the first conductivity type thin film;

the second conductivity type thin film including

a high-concentration layer having a first impurity concentration,

a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration,

a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration, and

a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration; and

a channel stop layer located at an ultimate end of the surface outer circumferential portion, the channel stop layer being connected to the first electric field diffusion layer, the channel stop layer having an impurity concentration higher than an impurity concentration of the first conductivity type thin film, the channel stop layer having a first conductivity type, and

a second electric field diffusion layer located between the first conductivity type thin film and the second conductivity type thin film, the second electric field diffusion layer having an impurity concentration higher than the impurity concentration of the first conductivity type thin film, the second electric field diffusion layer having the first conductivity type.

2. The semiconductor device according to claim 1, further comprising a plurality of embedded regions each located in the first electric field diffusion layer and having a second conductivity type, wherein respective widths of the plurality of embedded regions become smaller toward an outer circumference of the semiconductor device.

3. The semiconductor device according to claim 1, comprising a silicon carbide semiconductor element provided with a trench, wherein

the first conductivity type thin film includes a drift region of the silicon carbide semiconductor element, and

the second conductivity type thin film includes a body region of the silicon carbide semiconductor element.

4. The semiconductor device according to claim 1, comprising a silicon carbide semiconductor element provided with a trench, wherein the second electric field diffusion layer includes a trench current diffusion layer of the silicon carbide semiconductor element.