Structures and methods of fabricating dual gate devices

• US 10,453,953 B2
• Filed: 12/21/2016
• Issued: 10/22/2019
• Est. Priority Date: 03/02/2010
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Terrill, Kyle, Bai, Yuming, Pattanayak, Deva, Luo, Zhiyun
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US15/387,378
• Publication Number:
  US 20170104096A1
• Time in Patent Office: 1,035 Days
• Field of Search: 438424
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Claims

1. A semiconductor device comprising:

a substrate;

an epi region over said substrate;

a source trench that extends through said epi region and into said substrate;

a gate trench that extends into but not through said epi region, wherein sidewalls of said gate trench are parallel to sidewalls of said source trench;

a source contact coupled to first polysilicon in said source trench at an end of said source trench, wherein said source contact is directly over and in contact with a first surface of said first polysilicon; and

a gate contact coupled to second polysilicon in said gate trench at an end of said gate trench, wherein said gate contact is directly over and in contact with a second surface of said second polysilicon,

wherein said first and second surfaces are both flush with a surface of a mesa that is between said gate and source trenches, wherein a first oxide layer lines said source trench and a second oxide layer lines said gate trench, wherein a surface of said first oxide layer is flush with both said first and second surfaces and wherein a surface of second oxide layer is flush with both said first and second surfaces, wherein said source contact is also in contact with said mesa, and wherein said source contact is isolated from said second polysilicon in said gate trench by an oxide region above said second surface.

2. The semiconductor device of claim 1 wherein said source contact is part of a first metal layer and said gate contact is part of a second metal layer, wherein said first and second metal layers are physically isolated from one another and in the same surface plane.

3. The semiconductor device of claim 1 wherein said gate trench is wider at said second end.

4. The semiconductor device of claim 1 wherein said gate trench is wider than said gate contact.

5. The semiconductor device of claim 1 further comprising a region of p-type dopant adjacent an upper surface of said mesa between said gate and source trenches, wherein said source contact is also in contact with said region of p-type dopant.

6. A semiconductor device comprising:

a substrate;

an epi region over said substrate;

a source trench that extends through said epi region and into said substrate;

a gate trench that extends into but not through said epi region, wherein sidewalls of said gate trench are parallel to sidewalls of said source trench and wherein said source trench and said gate trench are separated by a mesa having an upper surface;

a source contact of a source metal layer coupled to and in contact with a first surface of first polysilicon in said source trench at an end of said source trench and also coupled to and in contact with said mesa, wherein said source metal layer formed on said substrate extends over said source trench, said mesa and said gate trench; and

a gate contact of a gate metal layer coupled to and in contact with a second surface of second polysilicon in said gate trench at an end of said gate trench, wherein said gate metal layer formed on said substrate extends over said source trench, said mesa and said gate trench and wherein said first surface and said second surface are each flush with said upper surface of said mesa on which said source metal layer and said gate metal layer are disposed, wherein a first oxide layer lines said source trench and wherein a second oxide layer lines said gate trench, wherein a surface of said first oxide layer is flush with both said first said surface and said second surface and wherein a surface of second oxide layer is flush with both said first surface and said second surface, and wherein said source metal layer is isolated from said second polysilicon in said gate trench by an oxide region above said second surface.

7. The semiconductor device of claim 6 wherein said source and gate metal layers are physically isolated from one another and in the same surface plane.

8. The semiconductor device of claim 6 wherein said gate trench is wider at said second end.

9. The semiconductor device of claim 6 wherein said gate trench is wider than said gate contact.

10. The semiconductor device of claim 6 further comprising a region of p-type dopant adjacent said upper surface of said mesa between said gate and source trenches, wherein said source contact is also in contact with said region of p-type dopant.