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Lateral DMOS device with dummy gate

  • US 10,453,955 B2
  • Filed: 01/12/2018
  • Issued: 10/22/2019
  • Est. Priority Date: 01/17/2012
  • Status: Active Grant
First Claim
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1. An integrated circuit device comprising:

  • a source region having a first conductivity type;

    a drain region having the first conductivity type;

    an interposed region between the source region and the drain region;

    a first gate dielectric over the interposed region;

    an active gate over the first gate dielectric, an entirety of the active gate being on the first gate dielectric;

    a second gate dielectric over the interposed region, the second gate dielectric being in direct contact with the first gate dielectric such that an upper surface of the first gate dielectric and an upper surface of the second gate dielectric form a step, wherein the second gate dielectric is thicker than the first gate dielectric, wherein a lower surface of the first gate dielectric is not planar with a lower surface of the second gate dielectric; and

    a dummy gate over the second gate dielectric, wherein the dummy gate is interposed between the active gate and the drain region, an entirety of the dummy gate being on the second gate dielectric, wherein the step is free of the active gate and the dummy gate.

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