Lateral DMOS device with dummy gate

• US 10,453,955 B2
• Filed: 01/12/2018
• Issued: 10/22/2019
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Liu, Ruey-Hsin, Cai, Jun, Chou, Hsueh-Liang, Chen, Chi-Chih
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US15/869,261
• Publication Number:
  US 20180138312A1
• Time in Patent Office: 648 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Claims

1. An integrated circuit device comprising:

a source region having a first conductivity type;

a drain region having the first conductivity type;

an interposed region between the source region and the drain region;

a first gate dielectric over the interposed region;

an active gate over the first gate dielectric, an entirety of the active gate being on the first gate dielectric;

a second gate dielectric over the interposed region, the second gate dielectric being in direct contact with the first gate dielectric such that an upper surface of the first gate dielectric and an upper surface of the second gate dielectric form a step, wherein the second gate dielectric is thicker than the first gate dielectric, wherein a lower surface of the first gate dielectric is not planar with a lower surface of the second gate dielectric; and

a dummy gate over the second gate dielectric, wherein the dummy gate is interposed between the active gate and the drain region, an entirety of the dummy gate being on the second gate dielectric, wherein the step is free of the active gate and the dummy gate.

2. The integrated circuit device of claim 1, further comprising a first well region, wherein the drain region has an interface with the first well region, the first well region having the first conductivity type.

3. The integrated circuit device of claim 2, further comprising a second well region within the first well region, wherein the source region has an interface with the second well region, the second well region having a second conductivity type.

4. The integrated circuit device of claim 3, wherein the active gate overlaps an interface between the first well region and the second well region.

5. The integrated circuit device of claim 2, wherein the dummy gate is over the first well region.

6. The integrated circuit device of claim 5, wherein a bottom surface of the second gate dielectric contacts the first well region.

7. The integrated circuit device of claim 1, further comprising a doped region having a second conductivity type, the source region being interposed between doped region and the active gate.

8. The integrated circuit device of claim 7, further comprising a contact extending over an interface between the doped region and the source region.

9. An integrated circuit device comprising:

a source region having a first conductivity type;

a drain region having the first conductivity type;

a first doped region having a second conductivity type, the first doped region being interposed between the source region and the drain region;

a drift region having the first conductivity type, the drift region being interposed between the first doped region and the drain region;

a first gate dielectric over the first doped region;

an active gate over the first gate dielectric, an entirety of the first gate dielectric under the active gate having a first uniform thickness;

a second gate dielectric over the drift region, wherein the second gate dielectric is thicker than the first gate dielectric, wherein a step is formed at an interface between the first gate dielectric and the second gate dielectric; and

a dummy gate over the second gate dielectric, an entirety of the second gate dielectric under the dummy gate having a second uniform thickness, wherein the step is free of the active gate and the dummy gate.

10. The integrated circuit device of claim 9, wherein the drift region extends below the source region.

11. The integrated circuit device of claim 10, further comprising a second doped region having the second conductivity type, the second doped region having a higher concentration of P-type dopants that the first doped region, the source region being interposed between the first doped region and the second doped region.

12. The integrated circuit device of claim 11, wherein an entire bottom surface of the second doped region and an entire bottom surface of the source region contact the first doped region.

13. The integrated circuit device of claim 9, wherein a horizontal distance between the active gate and the dummy gate is in a range from 0.1 um to 1 um.

14. The integrated circuit device of claim 9, wherein a thickness of the first gate dielectric is between about 100 Å

and about 200 Å

.

15. The integrated circuit device of claim 14, wherein a thickness of the second gate dielectric is between about 500 Å

and about 1000 Å

.

16. A transistor comprising:

an extended drift region having a first conductivity type;

a drain region above the extended drift region, wherein the drain region has the first conductivity type;

a source region above the extended drift region, the source region having the first conductivity type;

a doped region interposed between the source region and the extended drift region, the doped region having a second conductivity type;

a first dielectric layer with a first thickness over the extended drift region;

a second dielectric layer with a second thickness over the extended drift region, wherein an upper surface of the first dielectric layer and an upper surface of the second dielectric layer form a step;

an active gate on the first dielectric layer, an entirety of the active gate being on the first dielectric layer; and

a dummy gate on the second dielectric layer, wherein the active gate is spaced apart from the dummy gate and the step, wherein an entirety of the dummy gate being on the second dielectric layer, and wherein the dummy gate is spaced apart from the step.

17. The transistor of claim 16, further comprising a body contact region, the body contact region having the second conductivity type.

18. The transistor of claim 17, further comprising a contact overlapping the source region and the body contact region.

19. The transistor of claim 16, wherein the first dielectric layer overlaps the extended drift region and the doped region.

20. The transistor of claim 19, wherein the active gate overlaps the extended drift region and the doped region.