Semiconductor device and manufacturing method for semiconductor device

• US 10,453,958 B2
• Filed: 08/09/2018
• Issued: 10/22/2019
• Est. Priority Date: 08/30/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Mori, Takahiro
• Primary Examiner(s): Tran, Trang Q
• Application Number:
  US16/059,855
• Publication Number:
  US 20190067476A1
• Time in Patent Office: 439 Days
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7846 the means being located in the lateral device isolation region, e.g. STI

Abstract

A semiconductor device includes a semiconductor substrate having a first surface and a second surface, a first insulation isolation film in which a first trench is formed and a conductive film having a gate electrode, a first buried part buried in the first trench and a first cap part located on the first buried part. The semiconductor substrate has a source region, a drain region, a drift region and a body region. The gate electrode faces the body region which is sandwiched between the drift region and the source region while being insulated from the body region. The first cap part projects longer than the first buried part in a channel width direction which is a direction along a boundary between the body region and the drift region in a planar view on the first insulation isolation film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a first surface and a second surface which is a surface opposite to the first surface;

a first insulation isolation film which is arranged in the first surface and in which a first trench which extends in a direction toward the second surface is formed; and

a conductive film having a gate electrode, a first buried part which is buried in the first trench and a first cap part which is located over the first buried part,

wherein the semiconductor substrate has a source region of a first conductivity type which is arranged in the first surface, a drain region of the first conductivity type which is arranged in the first surface separately from the source region, a drift region of the first conductivity type which is arranged in the first surface so as to surround the drain region and a body region of a second conductivity type which is a conductivity type opposite to the first conductivity type which is arranged in the first surface so as to be sandwiched between the drift region and the source region and to surround the source region,

wherein the gate electrode faces the body region which is sandwiched between the drift region and the source region while being insulated from the body region, and

wherein the first cap part projects from the first buried part in a channel width direction which is a direction along a boundary between the body region and the drift region in a planar view over the first insulation isolation film.

2. The semiconductor device according to claim 1 further comprising:

a second insulation isolation film which is arranged in the first surface and in which a second trench which extends in the direction toward the second surface is formed,

wherein the gate electrode further has a second buried part which is buried in the second trench and a second cap part which is located over the second buried part,

wherein a part of the drift region is sandwiched between the first insulation isolation film and the second insulation isolation film in the channel width direction, and

wherein the second cap part projects from the second buried part in the channel width direction over the second insulation isolation film.

3. The semiconductor device according to claim 2 further comprising:

a third insulation isolation film which is arranged in the first surface,

wherein the third insulation isolation film is located between the first insulation isolation film and the second insulation isolation film in the channel width direction.

4. The semiconductor device according to claim 2,

wherein bottoms of the first insulation isolation film and the second insulation isolation film are located in the drift region.

5. The semiconductor device according to claim 2,

wherein upper surfaces of the first cap part which is located over the first trench and of the second cap part which is located over the second trench are flat.

6. The semiconductor device according to claim 2,

wherein a maximum value of a thickness of the first insulation isolation film which is located between the drift region and the first buried part in the channel width direction is not more than 0.3 μ

m and a maximum value of a thickness of the second insulation isolation film which is located between the drift region and the second buried part in the channel width direction is not more than 0.3 μ

m.

7. The semiconductor device according to claim 2,

wherein a minimum value of a width of the part of the drift region which is sandwiched between the first insulation isolation film and the second insulation isolation film in the channel width direction is not more than 0.3 μ

m.

8. The semiconductor device according to claim 2,

wherein the first insulation isolation film is arranged more outward than an end of the drain region in the channel width direction, and

wherein the second insulation isolation film is arranged more inward than the end of the drain region.

9. The semiconductor device according to claim 2,

wherein a drain-region-side end of the gate electrode is arranged closer to the source region side than source-region-side ends of the first insulation isolation film and the second insulation isolation film.