Growth of cubic crystalline phase structure on silicon substrates and devices comprising the cubic crystalline phase structure

• US 10,453,996 B2
• Filed: 12/09/2016
• Issued: 10/22/2019
• Est. Priority Date: 05/04/2012
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute, UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Original Assignee: UNM Rainforest Innovations (f/k/a STC.UNM) (The University of New Mexico)
• Inventors: Brueck, Steven R. J., Lee, Seung-Chang, Wetzel, Christian, Durniak, Mark
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/374,547
• Publication Number:
  US 20170092485A1
• Time in Patent Office: 1,047 Days
• Field of Search: 257E21127, 257200, 257627, 257E33008, 257E33067, 257 13, 257 76, 257 77, 257 98, 438 44, 438700
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02395 Arsenides
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/02494 Structure
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02609 Crystal orientation
• CPC Class Codes: H01L 21/7806 involving the separation of the active layers from a substrate
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/18 within the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A method of forming a semiconductor structure includes providing a substrate comprising a first material portion and a single crystal silicon layer on the first material portion. The substrate further comprises a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface. A buffer layer is deposited in one or more of the plurality of grooves. A semiconductor material is epitaxially grown over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase.

Claims

1. A method of forming a semiconductor structure, the method comprising:

providing a substrate comprising a first material portion and a layer of single crystal silicon on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface;

depositing a buffer layer in one or more of the plurality of grooves;

epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer;

bonding a handle substrate to the epitaxially grown semiconductor material; and

removing the substrate including the layer of single crystal silicon from the epitaxially grown semiconductor material, and further removing the hexagonal crystalline phase layer.

2. The method of claim 1, further comprising depositing an insulating layer on the major front surface of the substrate prior to depositing the buffer layer, patterning the insulating layer to expose stripes of the substrate, and forming the plurality of grooves in the exposed stripes of the substrate.

3. The method of claim 1, wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate.

4. The method of claim 3, wherein the substrate is a silicon-on-insulator substrate comprising the layer of single crystal silicon over a buried insulator layer, the bottom portion of the truncated v-grooves comprising a portion of the layer of single crystal silicon.

6. The method of claim 3, wherein during the epitaxially growing of the semiconductor material a gap is formed between the hexagonal crystalline phase layer and the bottom portion of the truncated v-groove.

7. The method of claim 6, wherein at least a portion of the gap is filled with a gas.

8. The method of claim 6, wherein at least a portion of the gap is filled with a buffer layer material.

9. The method of claim 1, further comprising bonding the epitaxially grown semiconductor material to a second substrate.

10. The method of claim 1, further comprising forming a first electrode layer and a second electrode layer, both the first and second electrode layers providing for electrical contact with a semiconductor device comprising the cubic crystalline phase structure.

11. The method of claim 10, wherein the cubic crystalline phase structure has a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height so that the structure is tapered, gaps being formed adjacent to the tapered structure, the method further comprising depositing a filler material in the gaps.

12. The method of claim 11, wherein epitaxially growing the semiconductor material further comprising forming at least one quantum well in the cubic crystal material, the semiconductor device being a light emitting diode.

14. The method of claim 1, further comprising epitaxially growing a cubic crystal material from the cubic crystalline phase structure to form a continuous cubic crystal layer.

5. A method of forming a semiconductor structure, the method comprising:

providing a first substrate comprising a first material portion and a layer of single crystal silicon on the first material portion, the first substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface, wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the first substrate, and further wherein the first substrate is a silicon-on-insulator substrate comprising the layer of single crystal silicon over a buried insulator layer, the bottom portion of the truncated v-groove exposing a surface of the buried insulator layer;

depositing a buffer layer in one or more of the plurality of grooves;

epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer;

bonding a handle substrate to the epitaxially grown semiconductor material; and

removing the first substrate including the layer of single crystal silicon from the epitaxially grown semiconductor material.

13. A method of forming a semiconductor device, the method comprising:

providing a substrate comprising a first material portion and a layer of single crystal silicon on the first material portion, the substrate further comprising a major front surface, a major backside surface opposing the major front surface, and a plurality of grooves positioned in the major front surface;

depositing a buffer layer in one or more of the plurality of grooves;

epitaxially growing a semiconductor material over the buffer layer and in the one or more plurality of grooves, the epitaxially grown semiconductor material comprising a hexagonal crystalline phase layer and a cubic crystalline phase structure disposed over the hexagonal crystalline phase layer;

bonding a handle substrate to the epitaxially grown semiconductor material; and

removing the substrate including the layer of single crystal silicon from the epitaxially grown semiconductor material to expose the semiconductor material and buffer layer grown in the grooves, wherein the hexagonal crystalline phase layer and cubic crystalline phase structure together have a length dimension, a width dimension and a height dimension, the width dimension decreasing with the height to form a tapered structure; and

employing the tapered structure to form a semiconductor device, wherein at least a portion of the hexagonal crystalline phase layer remains as part of the semiconductor device.

15. The method of claim 13, further comprising depositing an insulating layer on the major front surface of the substrate prior to depositing the buffer layer, patterning the insulating layer to expose stripes of the substrate, and forming the plurality of grooves in the exposed stripes of the substrate.

16. The method of claim 13, wherein one or more of the plurality of grooves are truncated v-grooves, each truncated v-groove comprising a first diagonal sidewall, a second diagonal sidewall opposing the first diagonal sidewall, and a bottom portion that is parallel with the major front surface of the substrate.

17. The method of claim 16, wherein the substrate is a silicon-on-insulator substrate comprising the layer of single crystal silicon over a buried insulator layer, the bottom portion of the truncated v-grooves comprising a portion of the layer of single crystal silicon.

18. The method of claim 16, wherein during the epitaxially growing of the semiconductor material a gap is formed between the hexagonal crystalline phase layer and the bottom portion of the truncated v-groove.

19. The method of claim 18, wherein at least a portion of the gap is filled with a gas.

20. The method of claim 18, wherein at least a portion of the gap is filled with a buffer layer material.