System and method for circuit protection

• US 10,454,266 B2
• Filed: 10/24/2016
• Issued: 10/22/2019
• Est. Priority Date: 10/24/2016
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Norling, Karl, Huber, Erwin
• Primary Examiner(s): Jackson, Stephen W
• Application Number:
  US15/332,755
• Publication Number:
  US 20180115148A1
• Time in Patent Office: 1,093 Days
• Field of Search: None
• CPC Class Codes: H02H 1/0007 concerning the detecting means in general G01R or other subclasses of G01; reed switches H01H71/2445
• CPC Class Codes: H02H 3/20 responsive to excess voltage
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/24 the characteristic being amplitude

Abstract

A method for operating a gate driver circuit includes supplying power to the gate driver circuit from a power supply including a positive power supply voltage and a negative power supply voltage. The method also includes comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor. The method also includes operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage. The method also includes deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage.

Claims

1. A method for operating a gate driver circuit comprising:

supplying power to the gate driver circuit from a power supply comprising a positive power supply voltage and a negative power supply voltage;

comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor;

operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage based on the comparing; and

deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage based on the comparing.

2. The method of claim 1, wherein the trigger voltage is between about 0.1V and about 0.5V above the first voltage.

3. The method of claim 1, wherein the trigger voltage above the first voltage by less than a forward operating voltage of a diode.

4. The method of claim 1, wherein the output terminal of the transistor is an emitter terminal or a source terminal.

5. The method of claim 1, wherein the transistor is a MOSFET.

6. The method of claim 1, wherein comparing comprises:

dividing the negative power supply voltage with respect to a reference voltage to form a first divided voltage;

dividing the first voltage with respect to the reference voltage to form a second divided voltage; and

comparing the first divided voltage with the second divided voltage.

7. The method of claim 6, wherein:

dividing the negative power supply voltage with respect to the reference voltage comprises using a first voltage divider circuit comprising a first plurality of resistive elements; and

dividing the first voltage with respect to the reference voltage comprises using a second voltage divider circuit comprising a second plurality of resistive elements.

8. The method of claim 1, wherein comparing comprises using a comparator circuit.

9. The method of claim 8, further comprising limiting a voltage at an input terminal of the comparator circuit.

10. The method of claim 9, wherein limiting the voltage at the input terminal of the comparator circuit comprises using a clamp circuit coupled to the input terminal of the comparator circuit.

11. A gate driver circuit, comprising:

a first voltage reference terminal configured to be coupled to an output terminal of a transistor;

a voltage detection circuit coupled to a power supply terminal and the first voltage reference terminal, wherein the voltage detection circuit is configured to detect a first supply voltage condition, a second supply voltage condition, and a third supply voltage condition wherein;

in the first supply voltage condition, a voltage at the power supply terminal is negative relative to the voltage at the first voltage reference terminal;

in the second supply voltage condition, the voltage at the power supply terminal is positive relative to the voltage at the first voltage reference terminal and the voltage at the power supply terminal is less than a positive trigger voltage; and

in the third supply voltage condition, the voltage at the power supply terminal is positive relative to the voltage at the first voltage reference terminal and the voltage at the power supply terminal is greater than the positive trigger voltage; and

a shutdown circuit coupled to the voltage detection circuit, the shutdown circuit configured to deactivate at least a portion of the gate driver circuit when the voltage detection circuit detects the third supply voltage condition.

12. The circuit of claim 11, wherein the voltage detection circuit comprises a comparator having inputs coupled to the power supply terminal and the first voltage reference terminal.

13. The circuit of claim 12, wherein the voltage detection circuit further comprises:

a first voltage divider coupled between a second voltage reference terminal and the power supply terminal, wherein an output of the first voltage divider is coupled to a first input of the comparator; and

a second voltage divider coupled between the second voltage reference terminal and the first voltage reference terminal, wherein an output of the second voltage divider is coupled to a second input of the comparator.

14. The circuit of claim 13, wherein:

the first voltage divider comprises a first resistive element coupled between the first input of the comparator and the power supply terminal, and a second resistive element coupled between the first input of the comparator and the second voltage reference terminal; and

the second voltage divider comprises a third resistive element coupled between the second input of the comparator and the first voltage reference terminal, and a fourth resistive element coupled between the second input of the comparator and the second voltage reference terminal.

15. The circuit of claim 13, further comprising a voltage regulator coupled to the second voltage reference terminal, the voltage regulator configured to regulate the voltage at the second voltage reference terminal.

16. The circuit of claim 13, further comprising a second voltage reference supply circuit coupled to the second voltage reference terminal.

17. The circuit of claim 11, wherein the positive trigger voltage is less than a forward operating voltage of a diode.

18. The circuit of claim 11, wherein the power supply terminal is a first power supply terminal, and wherein the voltage detection circuit is coupled to a second power supply terminal different from the first power supply terminal.

19. The circuit of claim 11, wherein the transistor is an IGBT.

20. The circuit of claim 11, wherein the output terminal of the transistor is an emitter terminal or a source terminal.

21. A circuit comprising:

a voltage monitoring circuit, comprising;

a comparator;

a first voltage divider coupled between a reference voltage node and a first power supply terminal, wherein an output of the first voltage divider is coupled to a first input of the comparator; and

a second voltage divider coupled between the reference voltage node and an output terminal of a transistor, wherein an output of the second voltage divider is coupled to a second input of the comparator; and

a gate driver circuit coupled to the voltage monitoring circuit, wherein a portion of the gate driver circuit is configured to be active when the output of the comparator is in a first state, wherein the portion of the gate driver circuit is configured to be inactive when the output of the comparator is in a second state, wherein the output of the comparator is in the first state when the first power supply terminal has a voltage more negative than a positive trigger voltage, and wherein the output of the comparator is in the second state when the first power supply terminal has a voltage greater than or equal to the positive trigger voltage.

22. The circuit of claim 21, wherein the gate driver circuit is configured to be coupled to a gate terminal of the transistor.

23. The circuit of claim 21, wherein the transistor is an IGBT.

24. The circuit of claim 21, wherein the output terminal of the transistor is an emitter terminal or a source terminal.

25. The circuit of claim 21, wherein the positive trigger voltage is between about 0.1V and about 0.5V more positive than the voltage at the output terminal of the transistor.

26. The circuit of claim 21, wherein:

the first voltage divider comprises a first resistor coupled between the first input of the comparator and the first power supply terminal, and a second resistor coupled between the first input of the comparator and the reference voltage node; and

the second voltage divider comprises a third resistor coupled between the second input of the comparator and the output terminal of the transistor, and a fourth resistor coupled between the second input of the comparator and the reference voltage node.

27. The circuit of claim 26, further comprising a cascode transistor having a load path coupled between the third resistor and the output terminal of the transistor.

28. The circuit of claim 21, further comprising a filter circuit coupled to the first input of the comparator.

29. The circuit of claim 21, further comprising a voltage regulator coupled between a second power supply voltage terminal and the reference voltage node.

30. The circuit of claim 21, further comprising a clamp circuit coupled between a second power supply voltage terminal and the reference voltage node.