Method for driving a transistor device with non-isolated gate, drive circuit and electronic circuit

• US 10,454,456 B2
• Filed: 07/27/2018
• Issued: 10/22/2019
• Est. Priority Date: 08/25/2017
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Zojer, Bernhard
• Primary Examiner(s): Donovan, Lincoln D
• Assistant Examiner(s): Mattison, Dave
• Application Number:
  US16/047,672
• Publication Number:
  US 20190068173A1
• Time in Patent Office: 452 Days
• Field of Search: 327109
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption

Abstract

Disclosed is a method for driving a transistor device and an electronic circuit that includes a transistor device. The method includes driving the transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level. Driving the transistor device in the off-state includes: operating the transistor device in a first off-state after the drive signal changes from the on-level to the off-level; after the first off-state, operating the transistor device in a second off-state different from the first off-state; and after the second off-state, operating the transistor device in a third off-state different from the second off-state if the off-level of the drive signal prevails longer than a predefined maximum time period.

Claims

1. A method comprising:

driving a transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level,

wherein driving the transistor device in the off-state comprises;

operating the transistor device in a first off-state after the drive signal changes from the on-level to the off-level, wherein operating the transistor device in the first off-state comprises driving the transistor device with a first drive voltage,

after the first off-state, operating the transistor device in a second off-state different from the first off-state, wherein operating the transistor device in the second off-state comprises driving the transistor device with a second drive voltage, the second drive voltage being different than the first drive voltage, and

after the second off-state, operating the transistor device in a third off-state different from the second off-state in response to the off-level of the drive signal prevailing longer than a predefined maximum time period, wherein operating the transistor device in the third off-state comprises driving the transistor device with a third drive voltage, the third drive voltage being different than the second drive voltage,

wherein a difference between a threshold voltage of the transistor device and the first drive voltage is greater than a difference between the threshold voltage and the second drive voltage, and

wherein a difference between a threshold voltage of the transistor device and the third drive voltage is greater than the difference between the threshold voltage and the second drive voltage.

2. The method of claim 1,

wherein operating the transistor device in the first off-state comprises operating the transistor device in the first off-state for a predefined first time period.

3. The method of claim 2, wherein the second drive voltage is substantially zero.

4. The method of claim 1,

wherein driving the transistor device in the on-state comprises connecting a series circuit with a voltage source and an RC circuit between a control node and a first load node of the transistor device,

wherein operating the transistor device in the first off-state comprises connecting the RC circuit between the control node and the first load node of the transistor device, and

wherein operating the transistor device in the second off-state comprises connecting the control node and the first load node of the transistor device.

5. The method of claim 4,

wherein operating the transistor device in the third off-state comprises connecting the voltage source between the control node and the gate node such that the drive voltage in the on-state and the drive voltage in the third off-state have opposite polarities.

6. The method of claim 1, wherein the transistor device is a high electron mobility transistor (HEMT).

7. The method of claim 1, the method further comprising:

in an electronic circuit that includes the transistor device and an electronic switch, operating the electronic switch in a plurality of successive drive cycles such that in each drive cycle it operates in an on-state and, after the on-state, in an off-state, and operating the transistor device such that the electronic switch and the transistor device are operated in the on-state alternately.

8. The method of claim 7, further comprising:

operating the transistor device in a first dead time between the on-state of the electronic switch and the on-state of the transistor device and a second dead time between the on-state of the transistor device and the on-state of the electronic switch,

wherein a duration of the first dead time is selected from between 1.1 times and 2 times a duration of the second dead time.

9. The method of claim 7,

wherein operating the electronic switch comprises operating the electronic switch at a switching frequency selected from between a minimum switching frequency and a maximum switching frequency, and

wherein a duration of the maximum switching frequency is greater than a reciprocal of the minimum switching frequency.

10. The method of claim 9, wherein the duration of the maximum switching frequency is greater than 3 times a reciprocal of the minimum switching frequency.

11. A drive circuit configured to drive a transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level, wherein in the off-state the drive circuit is configured to drive the transistor device

in a first off-state with a first drive voltage after the drive signal changes from the on-level to the off-level,

after the first off-state, in a second off-state with a second drive voltage, wherein the second off-state is different from the first off-state and wherein the second drive voltage is different than the first drive voltage, and

after the second off-state, in a third off-state with a second drive voltage, wherein the third off-state is different from the second off-state and the third drive voltage is different than the second drive voltage, wherein the transistor device is driven in the third off state in response to the off-level of the drive signal prevailing longer than a predefined maximum time period,

wherein a difference between a threshold voltage of the transistor device and the first drive voltage is greater than a difference between the threshold voltage and the second drive voltage, and

wherein a difference between a threshold voltage of the transistor device and the third drive voltage is greater than the difference between the threshold voltage and the second drive voltage.

12. The drive circuit of claim 11,

wherein the drive circuit is configured to drive the transistor device in the first off-state for a predefined first time period.

13. The drive circuit of claim 11, wherein the second drive voltage is substantially zero.

14. The drive circuit of claim 12,

wherein the drive circuit comprises an RC circuit and is configured

to drive the transistor device in the on-state by connecting a series circuit with a voltage source and the RC circuit between a control node and a first load node of the transistor device,

to drive the transistor device in the first off-state by connecting the RC circuit between the control node and the first load node of the transistor device, and

to drive the transistor device in the second off-state by connecting the control node and the first load node of the transistor device.

15. The drive circuit of claim 14, wherein the drive circuit is further configured to drive the transistor device in the third off-state by connecting the voltage source between the control node and the gate node such that the drive voltage in the on-state and the drive voltage in the third off-state have opposite polarities.

16. The drive circuit of claim 14, wherein the RC circuit comprises:

a series circuit with a capacitor and a first resistor, and

a second resistor connected in parallel with the series circuit.

17. The drive circuit of claim 16, wherein a resistance of the second resistor is between 50 times and 200 times a resistance of the first resistor.

18. An electronic circuit, comprising:

a transistor device, wherein the transistor device is a high electron mobility transistor (HEMT); and

a drive circuit configured to drive the transistor device based on a drive signal such that the transistor device is driven in an on-state when the drive signal has an on-level and an off-state when the drive signal has an off-level, wherein in the off-state the drive circuit is configured to drive the transistor device

in a first off-state after the drive signal changes from the on-level to the off-level,

after the first off-state, in a second off-state different from the first off-state, and

after the second off-state, in a third off-state different from the second off-state if the off-level of the drive signal prevails longer than a predefined maximum time period.