Frequency compensation circuit used in DC voltage converter

• US 10,454,461 B1
• Filed: 08/16/2018
• Issued: 10/22/2019
• Est. Priority Date: 05/23/2018
• Status: Active Grant

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Yen, Tzu-Yang, Chen, Chih-Yuan
• Primary Examiner(s): Jager, Ryan
• Application Number:
  US16/103,966
• Time in Patent Office: 432 Days
• Field of Search: 327114
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 19/20 characterised by logic function, e.g. AND, OR, NOR, NOT circuits H03K19/003 - H03K19/01 take precedence
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 4/501 the starting point of the flyback period being determined by the amplitude of the voltage across the capacitor, e.g. by a comparator
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A frequency compensation circuit includes a compensation circuit and a calculation circuit. The compensation circuit controls the calculation circuit to generate a ramp voltage when the voltage at a node between an upper-side switch and a lower-side switch of the DC voltage converter is larger than an input voltage of the DC voltage converter. The calculation circuit generates a control signal at low level when the ramp voltage is smaller than the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at high level. The calculation generates the control signal at high level when the ramp voltage is larger than or equal to the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at low level.

Claims

1. A frequency compensation circuit, generating a constant on-time signal to a DC voltage converter to maintain switching frequencies of an upper-side switch and a lower-side switch of the DC voltage converter, comprising:

a calculation circuit, coupled to the DC voltage converter, generating a ramp voltage, and generating a control signal according to the ramp voltage and an output voltage of the DC voltage converter, such that the constant on-time signal is generated according to the control signal; and

a compensation circuit, coupled to the calculation circuit and the DC voltage converter, detecting the voltage at a node between the upper-side switch and the lower-side switch of the DC voltage converter, and controlling the calculation circuit to generate the ramp voltage according to an input voltage of the DC voltage converter and the voltage at the node;

wherein the compensation circuit controls the calculation circuit to generate the ramp voltage when the voltage at the node is larger than the input voltage of the DC voltage converter, the calculation circuit generates the control signal at low level when the ramp voltage is smaller than the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at high level, and the calculation circuit generates the control signal at high level when the ramp voltage is larger than or equal to the output voltage of the DC voltage converter so that the frequency compensation circuit generates the constant on-time signal at low level.

2. The frequency compensation circuit according to claim 1, wherein when the voltage at the node is smaller than or equal to the input voltage of the DC voltage converter, according to turning on and turning off of the upper-side switch and the lower-side switch of the DC voltage converter, the compensation circuit controls the calculation circuit to generate the ramp voltage.

3. The frequency compensation circuit according to claim 1, wherein the calculation circuit includes:

a first resistor, wherein one end of the first resistor receives the input voltage of the DC voltage converter;

a first comparator, wherein a non-inverting input end of the first comparator is coupled to the other end of the first resistor, an inverting input end of the first comparator receives the output voltage of the DC voltage converter, and an output end of the first comparator outputs the control signal; and

a first capacitor, wherein one end of the first capacitor is coupled to the other end of the first resistor, and the other end of the first capacitor is grounded.

4. The frequency compensation circuit according to claim 3, wherein the compensation circuit includes:

a second resistor, coupled between the first resistor and the first capacitor;

wherein the product of the resistance of the second resistor and the capacitance of the first capacitor is equal to a time segment during which the upper-side switch of the DC voltage converter is turned off but the lower-side switch of the DC voltage converter has not yet been turned on.

5. The frequency compensation circuit according to claim 4, wherein the compensation circuit further includes:

a first transistor, wherein a first end of the first transistor is coupled to the non-inverting input end of the first comparator, and a second end of the first transistor is grounded;

a second transistor, wherein a first end of the second transistor is coupled to the non-inverting input end of the first comparator, and a second end of the second transistor is coupled between the second resistor and the first capacitor; and

a first logic circuit and a second logic circuit, wherein according to the input voltage of the DC voltage converter and the voltage at the node, the first logic circuit generates a first switching signal and the second logic circuit generates a second switching signal;

wherein a control end of the first transistor receives the first switching signal, a control end of the second transistor receives the second switching signal, and the ramp voltage generated by the calculation circuit is controlled according to the turning on and turning off of the upper-side switch and the lower-side switch of the DC voltage converter.

6. The frequency compensation circuit according to claim 5, wherein the first logic circuit includes:

a flip-flop, wherein an output pin of the flip-flop is coupled to the control end of the first transistor, and a set pin of the flip-flop receives a set signal;

an OR gate, wherein an output end of the OR gate is coupled to a reset pin of the flip-flop, and one input end of the OR gate is coupled to a first trigger circuit; and

an AND gate, wherein an output end of the AND gate is coupled to the other input end of the OR gate, one input end of the AND gate is coupled to a second trigger circuit, and the other input end of the AND gate is coupled to an output end of a second comparator;

wherein the first trigger circuit generates a pulse when a control voltage of the upper-side switch varies from a low voltage to a high voltage, the second trigger circuit generates a pulse when a control voltage of the lower-side switch varies from a high voltage to a low voltage, an inverting input end of the second comparator receives the input voltage of the DC voltage converter, and a non-inverting input end of the second comparator receives the voltage at the node.

7. The frequency compensation circuit according to claim 6, wherein the second logic circuit includes:

a flip-flop, wherein an output pin of the flip-flop is coupled to the control end of the second transistor through an inverter, and a reset pin of the flip-flop receives a reset signal;

an AND gate, wherein an output end of the AND gate is coupled to a set pin of the flip-flop, one input end of the AND gate is coupled to a third trigger circuit, and the other input end of the AND gate is coupled to an output end of a second comparator;

wherein the third trigger circuit generates a pulse when a control voltage of the upper-side switch varies from a high voltage to a low voltage, the inverting input end of the second comparator receives the input voltage of the DC voltage converter, and the non-inverting input end of the second comparator receives the voltage at the node.

8. The frequency compensation circuit according to claim 7, wherein if the voltage at the node is smaller than or equal to the input voltage of the DC voltage converter, when the control voltage of the upper-side switch varies from a low voltage to a high voltage, the first transistor is turned off due to the pulse generated by the first trigger circuit, such that the calculation circuit starts to generate the ramp voltage.

9. The frequency compensation circuit according to claim 7, wherein if the voltage at the node is larger than the input voltage of the DC voltage converter, when the control voltage of the lower-side switch varies from a high voltage to a low voltage, the OR gate outputs a signal at high level due to the pulse generated by the second trigger circuit and thus the first transistor is turned off, such that the calculation circuit generates the ramp voltage early.

10. The frequency compensation circuit according to claim 7, wherein if the voltage at the node is larger than the input voltage of the DC voltage converter, when the control voltage of the upper-side switch varies from a high voltage to a low voltage, the second transistor is turned off due to a signal at high level outputted by the AND gate, such that the ramp voltage generated by the calculation circuit achieves the output voltage of the DC voltage converter earlier.