Data processing device and data processing method

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First Claim
1. A transmitting device for generating a digital television broadcast signal and for decreasing a signaltonoise power ratio of the generated digital television broadcast signal, the transmitting device comprising:
 circuitry configured to;
receive data to be transmitted in a digital television broadcast signal;
perform low density parity check (LDPC) encoding by an LDPC encoder circuit on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal;
the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors,the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits,the information matrix portion is represented by a parity check matrix initial value table, andthe parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
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Abstract
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In groupwise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 or 12/15 is interleaved in units of bit groups of 360 bits. In groupwise deinterleave, a sequence of the LDPC code that has undergone the groupwise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.
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Current Assignee
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Sponsoring Entity
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DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD  
Patent #
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Current Assignee
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Sponsoring Entity
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Apparatus and method for transmitting/receiving data in a communication system using structured low density parity check code  
Patent #
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Current Assignee
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Sponsoring Entity
Samsung Electronics Co. Ltd.

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD  
Patent #
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Current Assignee
Saturn Licensing LLC

Sponsoring Entity
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TRANSMITTER APPARATUS AND SIGNAL PROCESSING METHOD THEREOF  
Patent #
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Current Assignee
Samsung Electronics Co. Ltd.

Sponsoring Entity
Samsung Electronics Co. Ltd.

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD  
Patent #
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Filed 06/03/2014

Current Assignee
Saturn Licensing LLC

Sponsoring Entity
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DATA PROCESSING DEVICE AND DATA PROCESSING METHOD  
Patent #
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Filed 09/12/2014

Current Assignee
Saturn Licensing LLC

Sponsoring Entity
Saturn Licensing LLC

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD  
Patent #
US 20160197625A1
Filed 09/12/2014

Current Assignee
Saturn Licensing LLC

Sponsoring Entity
Sony Corporation

8 Claims
 1. A transmitting device for generating a digital television broadcast signal and for decreasing a signaltonoise power ratio of the generated digital television broadcast signal, the transmitting device comprising:
circuitry configured to; receive data to be transmitted in a digital television broadcast signal; perform low density parity check (LDPC) encoding by an LDPC encoder circuit on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal; the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 2. A method for generating a digital television broadcast signal and for decreasing a signaltonoise power ratio of the generated digital television broadcast signal, the method comprising:
receiving data to be transmitted in a digital television broadcast signal; performing low density parity check (LDPC) encoding, by an LDPC encoder circuit, on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal; the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 3. A receiving device for use in an environment where a signaltonoise power ratio of a received digital television broadcast signal can be reduced, the receiving device comprising:
a tuner configured to receive a digital television broadcast signal including a timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word; and circuitry configured to deinterleave in a time direction by time deinterleaving the timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word to generate a mapped groupwise interleaved LDPC code word; demap the mapped groupwise interleaved LDPC code word to produce a groupwise interleaved LDPC code word, wherein each unit of 4 bits of the groupwise interleaved LDPC code word is mapped to one of 16 signal points of a modulation scheme; deinterleave the groupwise interleaved LDPC code word in units of bit groups of 360 bits to produce an LDPC code word; decode the LDPC code word; and process the decoded LDPC code word for presentation, wherein input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal, the LDPC code includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 4. A method for use by a receiving device in an environment where a signaltonoise power ratio of a digital television broadcast signal can be reduced, the method comprising:
receiving, by a tuner, a digital television broadcast signal including a timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word; deinterleaving the timeinterleaved mapped groupwise interleaved LDPC code word in a time direction to generate a mapped groupwise interleaved LDPC code word; demapping the mapped groupwise interleaved LDPC code word to produce a groupwise interleaved LDPC code word, wherein each unit of 4 bits of the groupwise interleaved LDPC code word is mapped to one of 16 signal points of a modulation scheme; deinterleaving the groupwise interleaved LDPC code word in units of bit groups of 360 bits to produce an LDPC code word; decoding, by decoding circuitry, the LDPC code word; and processing the decoded LDPC code word for presentation, wherein input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal, the LDPC code includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 5. A transmitting device for generating a digital television broadcast signal and for decreasing a signaltonoise power ratio of the generated digital television broadcast signal, the transmitting device comprising:
circuitry configured to; receive data to be transmitted in a digital television broadcast signal; perform low density parity check (LDPC) encoding by an LDPC encoder circuit on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal; the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 6. A method for generating a digital television broadcast signal and for decreasing a signaltonoise power ratio of the generated digital television broadcast signal, the method comprising:
receiving data to be transmitted in a digital television broadcast signal; performing low density parity check (LDPC) encoding, by an LDPC encoder circuit, on input bits of the received data according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15 to generate an LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal; the LDPC code includes information bits and parity bits, the parity bits being processed by a receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 7. A receiving device for use in an environment where a signaltonoise power ratio of a received digital television broadcast signal can be reduced, the receiving device comprising:
a tuner configured to receive a digital television broadcast signal including a timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word; and circuitry configured to deinterleave in a time direction by time deinterleaving the timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word to generate a mapped groupwise interleaved LDPC code word; demap the mapped groupwise interleaved LDPC code word to produce a groupwise interleaved LDPC code word, wherein each unit of 4 bits of the groupwise interleaved LDPC code word is mapped to one of 16 signal points of a modulation scheme; deinterleave the groupwise interleaved LDPC code word in units of bit groups of 360 bits to produce an LDPC code word; decode the LDPC code word; and process the decoded LDPC code word for presentation, wherein input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal, the LDPC code includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
 8. A method for use by a receiving device in an environment where a signaltonoise power ratio of a digital television broadcast signal can be reduced, the method comprising:
receiving, by a tuner, a digital television broadcast signal including a timeinterleaved mapped groupwise interleaved low density parity check (LDPC) code word; deinterleaving the timeinterleaved mapped groupwise interleaved LDPC code word in the time direction to generate a mapped groupwise interleaved LDPC code word; demapping the mapped groupwise interleaved LDPC code word to produce a groupwise interleaved LDPC code word, wherein each unit of 4 bits of the groupwise interleaved LDPC code word is mapped to one of 16 signal points of a modulation scheme; deinterleaving the groupwise interleaved LDPC code word in units of bit groups of 360 bits to produce an LDPC code word; decoding, by decoding circuitry, the LDPC code word; and processing the decoded LDPC code word for presentation, wherein input bits of data to be transmitted in the digital television broadcast signal are LDPC encoded according to a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15 to generate the LDPC code word, the LDPC code enabling error correction processing to correct errors generated in a transmission path of the digital television broadcast signal, the LDPC code includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors, the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table, having each row indicating positions of elements ‘
1’
in corresponding 360 columns of the information matrix portion as a subset of information bits used in calculating the parity bits in the LDPC encoding, is as follows
1 Specification
The present technology relates to a data processing device and a data processing method, and more particularly, a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code, for example.
Some of the information disclosed in this specification and the drawings was provided by Samsung Electronics Co, Ltd. (hereinafter referred to as Samsung), LG Electronics Inc., NERC, and CRC/ETRI (indicated in the drawings).
A low density parity check (LDPC) code has a high error correction capability, and in recent years, the LDPC code has widely been employed in transmission schemes of digital broadcasting such as Digital Video Broadcasting (DVB)S.2, DVBT.2, and DVBC.2 of Europe and the like, or Advanced Television Systems Committee (ATSC) 3.0 of the USA and the like (for example, see NonPatent Literature 1).
From a recent study, it is known that performance near a Shannon limit is obtained from the LDPC code when a code length increases, similar to a turbo code. Because the LDPC code has a property that a shortest distance is proportional to the code length, the LDPC code has advantages of a block error probability characteristic being superior and a socalled error floor phenomenon observed in a decoding characteristic of the turbo code being rarely generated, as characteristics thereof.
 NonPatent Literature 1: DVBS.2: ETSI EN 302 307 V1.2.1 (2009 August)
In data transmission using the LDPC code, for example, the LDPC code is converted into a symbol of an orthogonal modulation (digital modulation) such as Quadrature Phase Shift Keying (QPSK), and the symbol is mapped to a signal point of the orthogonal modulation and transmitted.
The data transmission using the LDPC code has spread worldwide, and there is a demand to secure excellent communication (transmission) quality.
The present technology was made in light of the foregoing, and it is desirable to secure excellent communication quality in data transmission using the LDPC code.
A first data processing device/method according to the present technology is a data processing device/method including: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15; a groupwise interleaving unit/step configured to perform groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits, wherein in the groupwise interleave. An (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
The LDPC code includes an information bit and a parity bit, the parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
In the first data processing device/method, LDPC encoding is performed based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15, groupwise interleave of interleaving the LDPC code is performed in units of bit groups of 360 bits, and the LDPC code is mapped to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
A second data processing device/method according to the present technology is a data processing device/method including: a groupwise deinterleaving unit/step configured to restore a sequence of an LDPC code that has undergone groupwise interleave and has been obtained from data transmitted from a transmitting device to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15, a groupwise interleaving unit configured to perform the groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
In the second data processing device, a sequence of an LDPC code that has undergone groupwise interleave and has been obtained from data transmitted from a transmitting device is restored to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 16200 bits and an encoding rate r is 10/15, a groupwise interleaving unit configured to perform the groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
A third data processing device/method according to the present technology is a data processing device/method including: an encoding unit/step configured to perform LDPC encoding based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15; a groupwise interleaving unit/step configured to perform groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits; and a mapping unit/step configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
In the third data processing device/method, LDPC encoding is performed based on a parity check matrix of an LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, groupwise interleave of interleaving the LDPC code is performed in units of bit groups of 360 bits, and the LDPC code is mapped to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
A fourth data processing device/method according to the present technology is a data processing device/method including: a groupwise deinterleaving unit/step configured to restore a sequence of an LDPC code that has undergone groupwise interleave and has been obtained from data transmitted from a transmitting device to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, a groupwise interleaving unit configured to perform the groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
In the fourth data processing device, a sequence of an LDPC code that has undergone groupwise interleave and has been obtained from data transmitted from a transmitting device is restored to an original sequence, the transmitting device including an encoding unit configured to perform LDPC encoding based on a parity check matrix of the LDPC code in which a code length N is 16200 bits and an encoding rate r is 12/15, a groupwise interleaving unit configured to perform the groupwise interleave of interleaving the LDPC code in units of bit groups of 360 bits, and a mapping unit configured to map the LDPC code to any of 16 signal points decided in a modulation scheme in units of 4 bits. In the groupwise interleave, when an (i+1)th bit group from a head of the LDPC code is indicated by a bit group i, a sequence of bit groups 0 to 44 of the LDPC code of 16200 bits is interleaved into a sequence of bit groups
3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
The LDPC code includes an information bit and a parity bit. The parity check matrix includes an information matrix portion corresponding to the information bit and a parity matrix portion corresponding to the parity bit. The information matrix portion is represented by a parity check matrix initial value table. The parity check matrix initial value table is a table in which a position of a 1 element of the information matrix portion is indicated for every 360 columns, and includes
The data processing device may be an independent device and may be an internal block constituting one device.
According to the present technology, it is possible to secure excellent communication quality in data transmission using the LDPC code.
The effects described herein are not necessarily limited and may include any effect described in the present disclosure.
Hereinafter, exemplary embodiments of the present technology will be described, but before the description of the exemplary embodiments of the present technology, an LDPC code will be described.
<LDPC Code>
The LDPC code is a linear code and it is not necessary for the LDPC code to be a binary code. However, in this case, it is assumed that the LDPC code is the binary code.
A maximum characteristic of the LDPC code is that a parity check matrix defining the LDPC code is sparse. In this case, the sparse matrix is a matrix in which the number of “1” of elements of the matrix is very small (a matrix in which most elements are 0).
In the parity check matrix H of
In encoding using the LDPC code (LDPC encoding), for example, a generation matrix G is generated on the basis of the parity check matrix H and the generation matrix G is multiplied by binary information bits, so that a code word (LDPC code) is generated.
Specifically, an encoding device that performs the LDPC encoding first calculates the generation matrix G in which an expression GH^{T}=0 is realized, between a transposed matrix H^{T }of the parity check matrix H and the generation matrix G. In this case, when the generation matrix G is a K×N matrix, the encoding device multiplies the generation matrix G with a bit string (vector u) of information bits including K bits and generates a code word c (=uG) including N bits. The code word (LDPC code) that is generated by the encoding device is received at a reception side through a predetermined communication path.
The LDPC code can be decoded by an algorithm called probabilistic decoding suggested by Gallager, that is, a message passing algorithm using belief propagation on a socalled Tanner graph, including a variable node (also referred to as a message node) and a check node. Hereinafter, the variable node and the check node are appropriately referred to as nodes simply.
Hereinafter, a real value (a reception LLR) that is obtained by representing the likelihood of “0” of a value of an ith code bit of the LDPC code (one code word) received by the reception side by a log likelihood ratio is appropriately referred to as a reception value u_{0i}. In addition, a message output from the check node is referred to as u_{j }and a message output from the variable node is referred to as v_{i}.
First, in decoding of the LDPC code, as illustrated in
Here, d_{v }and d_{c }in an expression (1) and expression (2) are respectively parameters which can be arbitrarily selected and illustrates the number of “1” in the longitudinal direction (column) and transverse direction (row) of the parity check matrix H. For example, in the case of an LDPC code ((3, 6) LDPC code) with respect to the parity check matrix H with a column weight of 3 and a row weight of 6 as illustrated in
In the variable node operation of the expression (1) and the check node operation of the expression (2), because a message input from an edge (line coupling the variable node and the check node) for outputting the message is not an operation target, an operation range becomes 1 to d_{v}−1 or 1 to d_{c}−1. The check node operation of the expression (2) is performed actually by previously making a table of a function R (v_{1}, v_{2}) represented by an expression (3) defined by one output with respect to two inputs v_{1 }and v_{2 }and using the table consecutively (recursively), as represented by an expression (4).
[Math. 3]
x=2 tan h^{−1}{tan h(v_{1}/2)tan h(v_{2}/2)}=R(v_{1},v_{2}) (3)
[Math. 4]
u_{j}=R(v_{1},R(v_{2},R(v_{3}, . . . R(v_{d}_{o}_{−2},v_{d}_{o}_{−1})))) (4)
In step S12, the variable k is incremented by “1” and the processing proceeds to step S13. In step S13, it is determined whether the variable k is more than the predetermined repetition decoding number of times C. When it is determined in step S13 that the variable k is not more than C, the processing returns to step S12 and the same processing is repeated hereinafter.
When it is determined in step S13 that the variable k is more than C, the processing proceeds to step S14, the message v_{i }that corresponds to a decoding result to be finally output is calculated by performing an operation represented by an expression (5) and is output, and the decoding processing of the LDPC code ends.
In this case, the operation of the expression (5) is performed using messages u_{j }from all edges connected to the variable node, different from the variable node operation of the expression (1).
In the parity check matrix H of
In
That is, when an element of a jth row and an ith column of the parity check matrix is 1, in
In a sum product algorithm that is a decoding method of the LDPC code, the variable node operation and the check node operation are repetitively performed.
In the variable node, the message v_{i }that corresponds to the edge for calculation is calculated by the variable node operation of the expression (1) using messages u_{1 }and u_{2 }from the remaining edges connected to the variable node and the reception value u_{0i}. The messages that correspond to the other edges are also calculated by the same method.
In this case, the check node operation of the expression (2) can be rewritten by an expression (6) using a relation of an expression a×b=exp{ln(a)+ln(b)}×sign(a)×sign(b). However, sign(x) is 1 in the case of x≥0 and is −1 in the case of x<0.
In x≥0, if a function ϕ(x) is defined as an expression ϕ(x)=ln(tan h(x/2)), an expression ϕ^{−1}(x)=2 tan h^{−1}(e^{−x}) is realized. For this reason, the expression (6) can be changed to an expression (7).
In the check node, the check node operation of the expression (2) is performed according to the expression (7).
That is, in the check node, as illustrated in
The function ϕ(x) of the expression (7) can be represented as ϕ(x)=ln((e^{x}+1)/(e^{x}−1)) and ϕ(x)=ϕ^{−1}(x) is satisfied in x>0. When the functions ϕ(x) and ϕ^{−1}(x) are mounted to hardware, the functions ϕ(x) and ϕ^{−1}(x) may be mounted using an LUT (Look Up Table). However, both the functions ϕ(x) and ϕ^{−1}(x) become the same LUT.
<Configuration Example of Transmission System to which Present Disclosure is Applied>
In
For example, the transmitting device 11 transmits (broadcasts) (transfers) a program of television broadcasting, and so on. That is, for example, the transmitting device 11 encodes target data that is a transmission target such as image data and audio data as a program into LDPC codes, and, for example, transmits them through a communication path 13 such as a satellite circuit, a ground wave and a cable (wire circuit).
The receiving device 12 receives the LDPC code transmitted from the transmitting device 11 through the communication path 13, decodes the LDPC code to obtain the target data, and outputs the target data.
In this case, it is known that the LDPC code used by the transmission system of
Meanwhile, in the communication path 13, burst error or erasure may be generated. Especially in the case where the communication path 13 is the ground wave, for example, in an OFDM (Orthogonal Frequency Division Multiplexing) system, power of a specific symbol may become 0 (erasure) according to delay of an echo (paths other than a main path), under a multipath environment in which D/U (Desired to Undesired Ratio) is 0 dB (power of Undesired=echo is equal to power of Desired=main path).
In the flutter (communication path in which delay is 0 and an echo having a Doppler frequency is added), when D/U is 0 dB, entire power of an OFDM symbol at a specific time may become 0 (erasure) by the Doppler frequency.
In addition, the burst error may be generated due to a situation of a wiring line from a receiving unit (not illustrated in the drawings) of the side of the receiving device 12 such as an antenna receiving a signal from the transmitting device 11 to the receiving device 12 or instability of a power supply of the receiving device 12.
Meanwhile, in decoding of the LDPC code, in the variable node corresponding to the column of the parity check matrix H and the code bit of the LDPC code, as illustrated in
In the decoding of the LDPC code, in the check node, the check node operation of the expression (7) is performed using the message calculated by the variable node connected to the check node. For this reason, if the number of check nodes in which error (including erasure) is generated simultaneously in (the code bits of the LDPC codes corresponding to) the plurality of connected variable nodes increases, decoding performance is deteriorated.
That is, if the two or more variable nodes of the variable nodes connected to the check node become simultaneously erasure, the check node returns a message in which the probability of a value being 0 and the probability of a value being 1 are equal to each other, to all the variable nodes. In this case, the check node that returns the message of the equal probabilities does not contribute to one decoding processing (one set of the variable node operation and the check node operation). As a result, it is necessary to increase the repetition number of times of the decoding processing, the decoding performance is deteriorated, and consumption power of the receiving device 12 that performs decoding of the LDPC code increases.
Therefore, in the transmission system of
<Configuration Example of Transmitting Device 11>
In the transmitting device 11, one or more input streams corresponding to target data are supplied to a mode adaptation/multiplexer 111.
The mode adaptation/multiplexer 111 performs mode selection and processes such as multiplexing of one or more input streams supplied thereto, as needed, and supplies data obtained as a result to a padder 112.
The padder 112 performs necessary zero padding (insertion of Null) with respect to the data supplied from the mode adaptation/multiplexer 111 and supplies data obtained as a result to a BB scrambler 113.
The BB scrambler 113 performs baseband scrambling (BB scrambling) with respect to the data supplied from the padder 112 and supplies data obtained as a result to a BCH encoder 114.
The BCH encoder 114 performs BCH encoding with respect to the data supplied from the BB scrambler 113 and supplies data obtained as a result as LDPC target data to be an LDPC encoding target to an LDPC encoder 115.
The LDPC encoder 115 performs LDPC encoding according to a parity check matrix or the like in which a parity matrix to be a portion corresponding to a parity bit of an LDPC code becomes a staircase (dual diagonal) structure with respect to the LDPC target data supplied from the BCH encoder 114, for example, and outputs an LDPC code in which the LDPC target data is information bits.
That is, the LDPC encoder 115 performs the LDPC encoding to encode the LDPC target data with an LDPC such as the LDPC code (corresponding to the parity check matrix) defined in the predetermined standard of the DVBS.2, the DVBT.2, the DVBC.2 or the like, and the LDPC code (corresponding to the parity check matrix) or the like that is to be employed in ATSC 3.0, and outputs the LDPC code obtained as a result.
The LDPC code defined in the standard of the DVBT.2 and the LDPC code that is to be employed in ATSC 3.0 are an IRA (Irregular Repeat Accumulate) code and a parity matrix of the parity check matrix of the LDPC code becomes a staircase structure. The parity matrix and the staircase structure will be described later. The IRA code is described in “Irregular RepeatAccumulate Codes”, H. Jin, A. Khandekar, and R. J. McEliece, in Proceedings of 2nd International Symposium on Turbo codes and Related Topics, pp. 18, September 2000, for example.
The LDPC code that is output by the LDPC encoder 115 is supplied to the bit interleaver 116.
The bit interleaver 116 performs bit interleave to be described later with respect to the LDPC code supplied from the LDPC encoder 115 and supplies the LDPC code after the bit interleave to an mapper 117.
The mapper 117 maps the LDPC code supplied from the bit interleaver 116 to a signal point representing one symbol of orthogonal modulation in a unit (symbol unit) of code bits of one or more bits of the LDPC code and performs the orthogonal modulation (multilevel modulation).
That is, the mapper 117 performs maps the LDPC code supplied from the bit interleaver 116 to a signal point determined by a modulation scheme performing the orthogonal modulation of the LDPC code, on an IQ plane (IQ constellation) defined by an I axis representing an I component of the same phase as a carrier and a Q axis representing a Q component orthogonal to the carrier, and performs the orthogonal modulation.
When the number of signal points decided in the modulation scheme of the orthogonal modulation performed by the mapper 117 is 2^{m}, mbit code bits of the LDPC code are used as a symbol (one symbol), and the mapper 117 maps the LDPC code supplied from the bit interleaver 116 to a signal point indicating a symbol among the 2^{m }signal points in units of symbols.
Here, examples of the modulation scheme of the orthogonal modulation performed by the mapper 117 include a modulation scheme specified in a standard such as DVBT.2, a modulation scheme that is scheduled to be employed in ATSC 3.0, and other modulation schemes, that is, includes Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), 8 PhaseShift Keying (8PSK), 16 Amplitude PhaseShift Keying (APSK), 32APSK, 16 Quadrature Amplitude Modulation (QAM), 16QAM, 64QAM, 256QAM, 1024QAM, 4096QAM, and 4 Pulse Amplitude Modulation (PAM). A modulation scheme by which the orthogonal modulation is performed in the mapper 117 is set in advance, for example, according to an operation of an operator of the transmitting device 11.
The data (a mapping result of mapping the symbol to the signal point) obtained by the process of the mapper 117 is supplied to a time interleaver 118.
The time interleaver 118 performs time interleave (interleave in a time direction) in a unit of symbol with respect to the data supplied from the mapper 117 and supplies data obtained as a result to an single input single output/multiple input single output encoder (SISO/MISO encoder) 119.
The SISO/MISO encoder 119 performs spatiotemporal encoding with respect to the data supplied from the time interleaver 118 and supplies the data to the frequency interleaver 120.
The frequency interleaver 120 performs frequency interleave (interleave in a frequency direction) in a unit of symbol with respect to the data supplied from the SISO/MISO encoder 119 and supplies the data to a frame builder/resource allocation unit 131.
On the other hand, for example, control data (signalling) for transfer control such as BB signaling (Base Band Signalling) (BB Header) is supplied to the BCH encoder 121.
The BCH encoder 121 performs the BCH encoding with respect to the signaling supplied thereto and supplies data obtained as a result to an LDPC encoder 122, similar to the BCH encoder 114.
The LDPC encoder 122 sets the data supplied from the BCH encoder 121 as LDPC target data, performs the LDPC encoding with respect to the data, and supplies an LDPC code obtained as a result to a mapper 123, similar to the LDPC encoder 115.
The mapper 123 maps the LDPC code supplied from the LDPC encoder 122 to a signal point representing one symbol of orthogonal modulation in a unit (symbol unit) of code bits of one or more bits of the LDPC code, performs the orthogonal modulation, and supplies data obtained as a result to the frequency interleaver 124, similar to the mapper 117.
The frequency interleaver 124 performs the frequency interleave in a unit of symbol with respect to the data supplied from the mapper 123 and supplies the data to the frame builder/resource allocation unit 131, similar to the frequency interleaver 120.
The frame builder/resource allocation unit 131 inserts symbols of pilots into necessary positions of the data (symbols) supplied from the frequency interleavers 120 and 124, configures a frame (for example, a physical layer (PL) frame, a T2 frame, a C2 frame, and so on) including symbols of a predetermined number from data (symbols) obtained as a result, and supplies the frame to an OFDM generating unit 132.
The OFDM generating unit 132 generates an OFDM signal corresponding to the frame from the frame supplied from the frame builder/resource allocation unit 131 and transmits the OFDM signal through the communication path 13 (
Here, for example, the transmitting device 11 can be configured without including part of the blocks illustrated in
<Configuration Example of Bit Interleaver 116>
The bit interleaver 116 has a function of interleaving data, and includes a parity interleaver 23, a groupwise interleaver 24, and a block interleaver 25.
The parity interleaver 23 performs parity interleave for interleaving the parity bits of the LDPC code supplied from the LDPC encoder 115 into positions of other parity bits and supplies the LDPC code after the parity interleave to the groupwise interleaver 24.
The groupwise interleaver 24 performs the groupwise interleave with respect to the LDPC code supplied from the parity interleaver 23 and supplies the LDPC code after the groupwise interleave to the block interleaver 25.
Here, in the groupwise interleave, 360 bits of one segment are used as a bit group, where the LDPC code of one code is divided into segments in units of 360 bits equal to the unit size P which will be described later, and the LDPC code supplied from the parity interleaver 23 is interleaved in units of bit groups, starting from the head.
When the groupwise interleave is performed, the error rate can be improved to be better than when the groupwise interleave is not performed, and as a result, it is possible to secure the excellent communication quality in the data transmission.
The block interleaver 25 performs block interleave for demultiplexing the LDPC code supplied from the groupwise interleaver 24, converts, for example, the LDPC code corresponding to one code into an mbit symbol serving as a unit of mapping, and supplies the mbit symbol to the mapper 117 (
Here, in the block interleave, for example, the LDPC code corresponding to one code is converted into the mbit symbol such that the LDPC code supplied from the groupwise interleaver 24 is written in a storage region in which columns serving as a storage region storing a predetermined number of bits in a column (vertical) direction are arranged in a row (horizontal) direction by the number m of bits of the symbol in the column direction and read from the storage region in the row direction.
<Parity Check Matrix H of the LDPC Code>
Next,
The parity check matrix H becomes an LDGM (LowDensity Generation Matrix) structure and can be represented by an expression H=[H_{A}H_{T}] (a matrix in which elements of the information matrix H_{A }are set to left elements and elements of the parity matrix H_{T }are set to right elements), using an information matrix H_{A }of a portion corresponding to information bits among the code bits of the LDPC code and a parity matrix H_{T }corresponding to the parity bits.
In this case, a bit number of the information bits among the code bits of one code of LDPC code (one code word) and a bit number of the parity bits are referred to as an information length K and a parity length M, respectively, and a bit number of the code bits of one code (one code word) of LDPC code is referred to as a code length N(=K+M).
The information length K and the parity length M of the LDPC code having the certain code length N are determined by an encoding rate. The parity check matrix H becomes a matrix in which row×column is M×N (a matrix of M×N). The information matrix H_{A }becomes a matrix of M×K and the parity matrix H_{T }becomes a matrix of M×M.
The parity matrix H_{T }of the parity check matrix H used for LDPC encoding in the LDPC encoder 115 is identical to, for example, the parity matrix H_{T }of the parity check matrix H of the LDPC code specified in a standard such as DVBT.2.
The parity matrix H_{T }of the parity check matrix H of the LDPC code that is defined in the standard of the DVBT.2 or the like becomes a staircase structure matrix (lower bidiagonal matrix) in which elements of 1 are arranged in a staircase shape, as illustrated in
As described above, the LDPC code of the parity check matrix H in which the parity matrix H_{T }becomes the staircase structure can be easily generated using the parity check matrix H.
That is, the LDPC code (one code word) is represented by a row vector c and a column vector obtained by transposing the row vector is represented by C^{T}. In addition, a portion of information bits of the row vector c to be the LDPC code is represented by a row vector A and a portion of the parity bits is represented by a row vector T.
The row vector c can be represented by an expression c=[AT] (a row vector in which elements of the row vector A are set to left elements and elements of the row vector T are set to right elements), using the row vector A corresponding to the information bits and the row vector T corresponding to the parity bits.
In the parity check matrix H and the row vector c=[AT] corresponding to the LDPC code, it is necessary to satisfy an expression Hc^{T}=0. The row vector T that corresponds to the parity bits constituting the row vector c=[AT] satisfying the expression Hc^{T}=0 can be sequentially calculated by setting elements of each row to 0, sequentially (in order) from elements of a first row of the column vector Hc′ in the expression Hc^{T}=0, when the parity matrix H_{T }of the parity check matrix H=[H_{A}H_{T}] becomes the staircase structure illustrated in
The column weight becomes X with respect KX columns from a first column of the parity check matrix H of the LDPC code defined in the standard of the DVBT.2 or the like, becomes 3 with respect to the following K3 columns, becomes 2 with respect to the following (M−1) columns, and becomes 1 with respect to a final column.
In this case, KX+K3+M−1+1 is equal to the code length N.
In the standard of the DVBT.2 or the like, LDPC codes that have code lengths N of 64800 bits and 16200 bits are defined.
With respect to the LDPC code having the code length N of 64800 bits, 11 encoding rates (nominal rates) of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC code having the code length N of 16200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined.
Hereinafter, the code length N of the 64800 bits is referred to as 64 kbits and the code length N of the 16200 is referred to as 16 kbits.
With respect to the LDPC code, an error rate tends to be lower in a code bit corresponding to a column of which a column weight of the parity check matrix H is large.
In the parity check matrix H that is illustrated in
<Parity Interleave>
Next, the parity interleave by the parity interleaver 23 of
As illustrated in
Meanwhile, the LDPC code that is output by the LDPC encoder 115 of FIG. 8 is an IRA code, same as the LDPC code that is defined in the standard of the DVBT.2 or the like, and the parity matrix H_{T }of the parity check matrix H becomes a staircase structure, as illustrated in
That is, A of
In the parity matrix H_{T }with a staircase structure, elements of 1 are adjacent in each row (excluding the first row). Therefore, in the Tanner graph of the parity matrix H_{T}, two adjacent variable nodes corresponding to a column of two adjacent elements in which the value of the parity matrix H_{T }is 1 are connected with the same check node.
Therefore, when parity bits corresponding to two abovementioned adjacent variable nodes become errors at the same time by burst error and erasure, and so on, the check node connected with two variable nodes (variable nodes to find a message by the use of parity bits) corresponding to those two parity bits that became errors returns message that the probability with a value of 0 and the probability with a value of 1 are equal probability, to the variable nodes connected with the check node, and therefore the performance of decoding is deteriorated. Further, when the burst length (bit number of parity bits that continuously become errors) becomes large, the number of check nodes that return the message of equal probability increases and the performance of decoding is further deteriorated.
Therefore, the parity interleaver 23 (
Here, the information matrix H_{A }of the parity check matrix H corresponding to the LDPC code output by the LDPC encoder 115 has a cyclic structure, similarly to the information matrix of the parity check matrix H corresponding to the LDPC code specified in a standard such as DVBT.2.
The cyclic structure refers to a structure in which a certain column matches one obtained by cyclically shifting another column, and includes, for example, a structure in which a position of 1 of each row of P columns becomes a position obtained by cyclically shifting a first column of the P columns in the column direction by a predetermined value such as a value that is proportional to a value q obtained by dividing a parity length M for every P columns. Hereinafter, the P columns in the cyclic structure are referred to appropriately as a unit size.
As an LDPC code defined in a standard such as DVBT.2, as described in
The parity length M becomes a value other than primes represented by an expression M=q×P=q×360, using a value q different according to the encoding rate. Therefore, similar to the unit size P, the value q is one other than 1 and M among the divisors of the parity length M and is obtained by dividing the parity length M by the unit size P (the product of P and q to be the divisors of the parity length M becomes the parity length M).
As described above, when information length is assumed to be K, an integer equal to or greater than 0 and less than P is assumed to be x and an integer equal to or greater than 0 and less than q is assumed to be y, the parity interleaver 23 interleaves the K+qx+y+1th code bit among code bits of an LDPC code of N bits to the position of the K+Py+x+1th code bit as parity interleave.
Since both of the K+qx+y+1th code bit and the K+Py+x+1th code bit are code bits after the K+1th one, they are parity bits, and therefore the positions of the parity bits of the LDPC code are moved according to the parity interleave.
According to the parity interleave, (the parity bits corresponding to) the variable nodes connected to the same check node are separated by the unit size P, that is, 360 bits in this case. For this reason, when the burst length is less than 360 bits, the plurality of variable nodes connected to the same check node can be prevented from simultaneously becoming the error. As a result, tolerance against the burst error can be improved.
The LDPC code after the interleave for interleaving the (K+qx+y+1)th code bit into the position of the (K+Py+x+1)th code bit is matched with an LDPC code of a parity check matrix (hereinafter, referred to as a transformed parity check matrix) obtained by performing column replacement for replacing the (K+qx+y+1)th column of the original parity check matrix H with the (K+Py+x+1)th column.
In the parity matrix of the transformed parity check matrix, as illustrated in
Here, the pseudo cyclic structure is a structure in which the remaining portion excluding a part has the cyclic structure.
The transformed parity check matrix obtained by performing the column permutation corresponding to the parity interleave on the parity check matrix of the LDPC code specified in the standard such as DVBT.2 has the pseudo cyclic structure rather than the (perfect) cyclic structure since it is one 1 element short (it is a 0 element) in a portion (a shift matrix which will be described later) of a 360×360 matrix of a right top corner portion of the transformed parity check matrix.
The transformed parity check matrix for the parity check matrix of the LDPC code output by the LDPC encoder 115 has the pseudo cyclic structure, for example, similarly to the transformed parity check matrix for the parity check matrix of the LDPC code specified in the standard such as DVBT.2.
The transformed parity check matrix of
The LDPC encoder 115 awaits supply of the LDPC target data from the BCH encoder 114. In step S101, the LDPC encoder 115 encodes the LDPC target data with the LDPC code and supplies the LDPC code to the bit interleaver 116. The processing proceeds to step S102.
In step S102, the bit interleaver 116 performs the bit interleave on the LDPC code supplied from the LDPC encoder 115, and supplies the symbol obtained by the bit interleave to the mapper 117, and the process proceeds to step S103.
That is, in step S102, in the bit interleaver 116 (
The groupwise interleaver 24 performs the groupwise interleave on the LDPC code supplied from the parity interleaver 23, and supplies the resulting LDPC code to the block interleaver 25.
The block interleaver 25 performs the block interleave on the LDPC code that has undergone the groupwise interleave performed by the groupwise interleaver 24, and supplies the mbit symbol obtained as a result to the mapper 117.
In step S103, the mapper 117 maps the symbol supplied from the block interleaver 25 to any of the 2^{m }signal points decided in the modulation scheme of the orthogonal modulation performed by the mapper 117, performs the orthogonal modulation, and supplies data obtained as a result to the time interleaver 118.
As described above, by performing the parity interleave and the groupwise interleave, it is possible to improve the error rate when transmission is performed using a plurality of code bits of the LDPC code as one symbol.
Here, in
That is, both the parity interleave and the groupwise interleave can be performed by writing and reading of the code bits with respect to the memory and can be represented by a matrix to convert an address (write address) to perform writing of the code bits into an address (read address) to perform reading of the code bits.
Therefore, if a matrix obtained by multiplying a matrix representing the parity interleave and a matrix representing the groupwise interleave is calculated, the code bits are converted by the matrixes, the parity interleave is performed, and a groupwise interleave result of the LDPC code after the parity interleave can be obtained.
In addition to the parity interleaver 23 and the groupwise interleaver 24, the block interleaver 25 can be integrally configured.
That is, the block interleave executed by the block interleaver 25 can be represented by the matrix to convert the write address of the memory storing the LDPC code into the read address.
Therefore, if a matrix obtained by multiplying the matrix representing the parity interleave, the matrix representing the groupwise interleave, and the matrix representing the block interleave is calculated, the parity interleave, the groupwise interleave, and the block interleave can be collectively executed by the matrixes.
<Configuration Example of LDPC Encoder 115>
The LDPC encoder 122 of
As described in
With respect to the LDPC code having the code length N of 64800 bits, 11 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10 are defined. With respect to the LDPC code having the code length N of 16200 bits, 10 encoding rates of 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, and 8/9 are defined (
For example, the LDPC encoder 115 can perform encoding (error correction encoding) using the LDPC code of each encoding rate having the code length N of 64800 bits or 16200 bits, according to the parity check matrix H prepared for each code length N and each encoding rate.
The LDPC encoder 115 includes an encoding processing unit 601 and a storage unit 602.
The encoding processing unit 601 includes an encoding rate setting unit 611, an initial value table reading unit 612, a parity check matrix generating unit 613, an information bit reading unit 614, an encoding parity operation unit 615, an a control unit 616. The encoding processing unit 601 performs the LDPC encoding of LDPC target data supplied to the LDPC encoder 115 and supplies an LDPC code obtained as a result to the bit interleaver 116 (
That is, the encoding rate setting unit 611 sets the code length N and the encoding rate of the LDPC code, according to an operation of an operator.
The initial value table reading unit 612 reads a parity check matrix initial value table to be described later, which corresponds to the code length N and the encoding rate set by the encoding rate setting unit 611, from the storage unit 602.
The parity check matrix generating unit 613 generates a parity check matrix H by arranging elements of 1 of an information matrix H_{A }corresponding to an information length K (=information length N−parity length M) according to the code length N and the encoding rate set by the encoding rate setting unit 611 in the column direction with a period of 360 columns (unit size P), on the basis of the parity check matrix initial value table read by the initial value table reading unit 612, and stores the parity check matrix H in the storage unit 602.
The information bit reading unit 614 reads (extracts) information bits corresponding to the information length K, from the LDPC target data supplied to the LDPC encoder 115.
The encoding parity operation unit 615 reads the parity check matrix H generated by the parity check matrix generating unit 613 from the storage unit 602, and generates a code word (LDPC code) by calculating parity bits for the information bits read by the information bit reading unit 614 on the basis of a predetermined expression using the parity check matrix H.
The control unit 616 controls each block constituting the encoding processing unit 601.
In the storage unit 602, a plurality of parity check matrix initial value tables that correspond to the plurality of encoding rates illustrated in
In step S201, the encoding rate setting unit 611 determines (sets) the code length N and the encoding rate r to perform the LDPC encoding.
In step S202, the initial value table reading unit 612 reads the previously determined parity check matrix initial value table corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611, from the storage unit 602.
In step S203, the parity check matrix generating unit 613 calculates (generates) the parity check matrix H of the LDPC code of the code length N and the encoding rate r determined by the encoding rate setting unit 611, using the parity check matrix initial value table read from the storage unit 602 by the initial value table reading unit 612, supplies the parity check matrix to the storage unit 602, and stores the parity check matrix in the storage unit.
In step S204, the information bit reading unit 614 reads the information bits of the information length K (=N×r) corresponding to the code length N and the encoding rate r determined by the encoding rate setting unit 611, from the LDPC target data supplied to the LDPC encoder 115, reads the parity check matrix H calculated by the parity check matrix generating unit 613 from the storage unit 602, and supplies the information bits and the parity check matrix to the encoding parity operation unit 615.
In step S205, the encoding parity operation unit 615 sequentially operates parity bits of a code word c that satisfies an expression (8) using the information bits and the parity check matrix H that have been read from the information bit reading unit 614.
Hc^{T}=0 (8)
In the expression (8), c represents a row vector as the code word (LDPC code) and c^{T }represents transposition of the row vector c.
As described above, when a portion of the information bits of the row vector c as the LDPC code (one code word) is represented by a row vector A and a portion of the parity bits is represented by a row vector T, the row vector c can be represented by an expression c=[A/T], using the row vector A as the information bits and the row vector T as the parity bits.
In the parity check matrix H and the row vector c=[AT] corresponding to the LDPC code, it is necessary to satisfy an expression Hc^{T}=0. The row vector T that corresponds to the parity bits constituting the row vector c=[AT] satisfying the expression Hc^{T}=0 can be sequentially calculated by setting elements of each row to 0, sequentially from elements of a first row of the column vector Hc^{T }in the expression Hc^{T}=0, when the parity matrix H_{T }of the parity check matrix H=[H_{A}H_{T}] becomes the staircase structure illustrated in
If the encoding parity operation unit 615 calculates the parity bits T with respect to the information bits A from the information bit reading unit 614, the encoding parity operation unit 615 outputs the code word c=[A/T] represented by the information bits A and the parity bits T as an LDPC encoding result of the information bits A.
Then, in step S206, the control unit 616 determines whether the LDPC encoding ends. When it is determined in step S206 that the LDPC encoding does not end, that is, when there is LDPC target data to perform the LDPC encoding, the processing returns to step S201 (or step S204). Hereinafter, the processing of steps S201 (or step S204) to S206 is repeated.
When it is determined in step S206 that the LDPC encoding ends, that is, there is no LDPC target data to perform the LDPC encoding, the LDPC encoder 115 ends the processing.
As described above, the parity check matrix initial value table corresponding to each code length N and each encoding rate r is prepared and the LDPC encoder 115 performs the LDPC encoding of the predetermined code length N and the predetermined encoding rate r, using the parity check matrix H generated from the parity check matrix initial value table corresponding to the predetermined code length N and the predetermined encoding rate r.
<Example of the Parity Check Matrix Initial Value Table>
The parity check matrix initial value table is a table that represents positions of elements of 1 of the information matrix H_{A }(
That is, the parity check matrix initial value table represents at least positions of elements of 1 of the information matrix H_{A }for every 360 columns (unit size P).
Examples of the parity check matrix H include a parity check matrix in which the (whole) parity matrix H_{T }has the staircase structure, which is specified in DVBT.2 or the like and a parity check matrix in which a part of the parity matrix H_{T }has the staircase structure, and the remaining portion is a diagonal matrix (a unit matrix), which is proposed by CRC/ETRI.
Hereinafter, an expression scheme of a parity check matrix initial value table indicating the parity check matrix in which the parity matrix H_{T }has the staircase structure, which is specified in DVBT.2 or the like, is referred to as a DVB scheme, and an expression scheme of a parity check matrix initial value table indicating the parity check matrix proposed by CRC/ETRI is referred to as an ETRI scheme.
That is,
The parity check matrix generating unit 613 (
That I,
The parity check matrix initial value table in the DVB method is the table that represents the positions of the elements of 1 of the whole information matrix H_{A }corresponding to the information length K according to the code length N and the encoding rate r of the LDPC code for every 360 columns (unit size P). In the ith row thereof, row numbers (row numbers when a row number of a first row of the parity check matrix H is set to 0) of elements of 1 of a (1+360×(i−1)th column of the parity check matrix H are arranged by a number of column weights of the (1+360×(i−1)th column.
Here, since the parity matrix H_{T }(
A row number k+1 of the parity check matrix initial value table in the DVB method is different according to the information length K.
A relation of an expression (9) is realized between the information length K and the row number k+1 of the parity check matrix initial value table.
K=(k+1)×360 (9)
In this case, 360 of the expression (9) is the unit size P described in
In the parity check matrix initial value table of
Therefore, the column weights of the parity check matrix H that are calculated from the parity check matrix initial value table of
The first row of the parity check matrix initial value table of
The second row of the parity check matrix initial value table of
As described above, the parity check matrix initial value table represents positions of elements of 1 of the information matrix H_{A }of the parity check matrix H for every 360 columns.
The columns other than the (1+360×(i−1))th column of the parity check matrix H, that is, the individual columns from the (2+360×(i−1))th column to the (360×i)th column are arranged by cyclically shifting elements of 1 of the (1+360×(i−1))th column determined by the parity check matrix initial value table periodically in a downward direction (downward direction of the columns) according to the parity length M.
That is, the (2+360×(i−1))th column is obtained by cyclically shifting (1+360×(i−1))th column in the downward direction by M/360 (=q) and the next (3+360×(i−1))th column is obtained by cyclically shifting (1+360×(i−1))th column in the downward direction by 2×M/360 (=2×q) (obtained by cyclically shifting (2+360×(i−1))th column in the downward direction by M/360 (=q)).
If a numerical value of a jth column (jth column from the left side) of an ith row (ith row from the upper side) of the parity check matrix initial value table is represented as and a row number of the jth element of 1 of the wth column of the parity check matrix H is represented as H_{wj}, the row number H_{wj }of the element of 1 of the wth column to be a column other than the (1+360×(i−1))th column of the parity check matrix H can be calculated by an expression (10).
H_{wj}=mod {h_{i,j}+mod((w−1),P)×q,M) (10)
In this case, mod(x, y) means a remainder that is obtained by dividing x by y.
In addition, P is a unit size described above. In the present embodiment, for example, same as the standard of the DVBS.2, the DVBT.2, and the DVBC.2, P is 360. In addition, q is a value M/360 that is obtained by dividing the parity length M by the unit size P (=360).
The parity check matrix generating unit 613 (
The parity check matrix generating unit 613 (
The parity check matrix of the ETRI scheme is configured with an A matrix, a B matrix, a C matrix, a D matrix, and a Z matrix.
The A matrix is a g×K upper left matrix of the parity check matrix expressed by a predetermined value g and the information length K of the LDPC code (=the code length N×the encoding rate r).
The B matrix is a g×g matrix having the staircase structure adjacent to the right of the A matrix.
The C matrix is an (N−K−g)×(K+g) matrix adjacently below the A matrix and the B matrix.
The D matrix is an (N−K−g)×(N−K−g) unit matrix adjacent to the right of the C matrix.
The Z matrix is a g×(N−K−g) zero matrix (zero matrix) adjacent to the right of the B matrix.
In the parity check matrix of the ETRI scheme configured with the A to D matrices and the Z matrix, the A matrix and a portion of the C matrix configure an information matrix, and the B matrix, the remaining portion of the C matrix, the D matrix, and the Z matrix configure a parity matrix.
Further, since the B matrix is the matrix having the staircase structure, and the D matrix is the unit matrix, a portion (a portion of the B matrix) of the parity matrix of the parity check matrix of the ETRI scheme has the staircase structure, and the remaining portion (the portion of the D matrix) is the diagonal matrix (the unit matrix).
Similarly to the information matrix of the parity check matrix of the DVB scheme, the A matrix and the C matrix have the cyclic structure for every 360 columns (the unit size P), and the parity check matrix initial value table of the ETRI scheme indicates positions of 1 elements of the A matrix and the C matrix in units of 360 columns.
Here, as described above, since the A matrix, and a portion of the C matrix configure the information matrix, it can be said that the parity check matrix initial value table of the ETRI scheme that indicates positions of 1 elements of the A matrix and the C matrix in units of 360 columns indicates at least positions of 1 elements of the information matrix in units of 360 columns.
In other words,
The parity check matrix initial value table of the ETRI scheme is a table in which positions of 1 elements of the A matrix and the C matrix are indicated for each unit size P, and row numbers (row numbers when a row number of a first row of the parity check matrix is 0) of 1 elements of a (1+P×(i−1))th column of the parity check matrix that correspond in number to the column weight of the (1+P×(i−1))th column are arranged in an ith row.
Here, in order to simplify the description, the unit size P is assumed to be, for example, 5.
Further, parameters for the parity check matrix of the ETRI scheme include g=M_{1}, M_{2}, Q_{1}, and Q_{2}.
g=M_{1 }is a parameter for deciding the size of the B matrix and has a value that is a multiple of the unit size P. The performance of the LDPC code is changed by adjusting g=M_{1}, and g=M_{1 }is adjusted to a predetermined value when the parity check matrix is decided. Here, 15, which is three times the unit size P (=5), is assumed to be employed as g=M_{1}.
M_{2 }has a value M−M_{1 }obtained by subtracting M_{1 }from the parity length M.
Here, since the information length K is N×r=50×1/2=25, and the parity length M is N−K=50−25=25, M_{2 }is M−M_{1}=25−15=10.
Q_{1 }is obtained from the formula Q_{1}=M_{1}/P, and indicates the number of shifts (the number of rows) of the cyclic shift in the A matrix.
In other words, in each column other than the (1+P×(i−1))th column of the A matrix of the parity check matrix of the ETRI scheme, that is, in each of a (2+P×(i−1))th column to a (P×i)th column, 1 elements of a (1+360×(i−1))th column decided by the parity check matrix initial value table have periodically been cyclically shifted downward (downward in the column) and arranged, and Q_{1 }indicates the number of shifts the cyclic shift in the A matrix.
Q_{2 }is obtained from the formula Q_{2}=M_{2}/P, and indicates the number of shifts (the number of rows) of the cyclic shift in the C matrix.
In other words, in each column other than the (1+P×(i−1))th column of the C matrix of the parity check matrix of the ETRI scheme, that is, in each of a (2+P×(i−1))th column to a (P×i)th column, 1 elements of a (1+360×(i−1))th column decided by the parity check matrix initial value table have periodically been cyclically shifted downward (downward in the column) and arranged, and Q_{2 }indicates the number of shifts the cyclic shift in the C matrix.
Here, Q_{1 }is M_{1}/P=15/5=3, and Q_{2 }is M_{2}/P=10/5=2.
In the parity check matrix initial value table of
In other words, 2, 6, and 18 are arranged in the 1st row of the parity check matrix initial value table of
Here, in this case, the A matrix is a 15×25 (g×K) matrix, the C matrix is a 10×40 ((N−K−g)×(K+g)) matrix, rows having the row numbers of 0 to 14 in the parity check matrix are rows of the A matrix, and rows having the row numbers of 15 to 24 in the parity check matrix are rows of the C matrix.
Thus, among the rows having the row numbers of 2, 6, and 18 (hereinafter referred to as rows #2, #6, and #18), the rows #2 and #6 are the rows of the A matrix, and the row #18 is the row of the C matrix.
2, 10, and 19 are arranged in the 2nd row of the parity check matrix initial value table of
Here, in the 6 (=1+5×(2−1))th column of the parity check matrix, among the rows #2, #10, and #19, the rows #2 and #10 are the rows of the A matrix, and the row #19 is the row of the C matrix.
22 is arranged in the 3rd row of the parity check matrix initial value table of
Here, in the 11 (=1+5×(3−1))th column of the parity check matrix, the row #22 is the row of the C matrix.
Similarly, 19 in the 4th column of the parity check matrix initial value table of
As described above, the parity check matrix initial value table indicates the positions of the 1 elements of the A matrix and the C matrix of the parity check matrix for each unit size P (=5 columns).
In each column other than a (1+5×(i−1))th column of the A matrix and the C matrix of the parity check matrix, that is, in each of a (2+5×(i−1))th column to a (5×i)th column, the 1 elements of the (1+5×(i−1))th column decided by the parity check matrix initial value table have periodically been cyclically shifted downward (downward in the column) and arranged according to the parameters Q_{1 }and Q_{2}.
In other words, for example, in the (2+5×(i−1))th column of the A matrix, the (1+5×(i−1))th column has been cyclically shifted downward by Q_{1 }(=3), and in a (3+5×(i−1))th column, the (1+5×(i−1))th column has been cyclically shifted downward by 2×Q_{1 }(=2×3) (the (2+5×(i−1))th column has been cyclically shifted downward by Q_{1}).
Further, for example, in the (2+5×(i−1))th column of the C matrix, the (1+5×(i−1))th column has been cyclically shifted downward by Q_{2 }(=2), and in a (3+5×(i−1))th column, the (1+5×(i−1))th column has been cyclically shifted downward by 2×Q_{2 }(=2×2) (the (2+5×(i−1))th column has been cyclically shifted downward by Q_{2}).
In the A matrix of
Further, in each of a 2 (=2+5×(1−1))nd column to a 5 (=5+5×(1−1))th column, an immediately previous column has been cyclically shifted downward by Q_{1}=3.
Further, in the A matrix of
Further, in each of a 7 (=2+5×(2−1))th column to a 10 (=5+5×(2−1))th column, an immediately previous column has been cyclically shifted downward by Q_{1}=3.
The parity check matrix generating unit 613 (
In the C matrix of
Further, each of a 2 (=2+5×(1−1))nd column to a 5 (=5+5×(1−1))th column is one in which an immediately previous column has been cyclically shifted downward by Q_{2}=2.
Further, in the C matrix of
Further, in each of the 7 (=2+5×(2−1))th column to the 10 (=5+5×(2−1))th column, each of a 12 (=2+5×(3−1))th column to a 15 (=5+5×(3−1))th column, each of a 17 (=2+5×(4−1))th column to a 20 (=5+5×(4−1))th column, and each of a 22 (=2+5×(5−1))nd column to a 25 (=5+5×(5−1))th column, an immediately previous column has been cyclically shifted downward by Q_{2}=2.
The parity check matrix generating unit 613 (
Further, the parity check matrix generating unit 613 arranges the Z matrix at the right of the B matrix, arranges the D matrix at the right of the C matrix, and generates the parity check matrix illustrated in
After generating the parity check matrix of
(The encoding parity operation unit 615 (
Here, the LDPC code generated using the parity check matrix of
The LDPC encoder 115 can perform LDPC encoding (generation of the LDPC code) using the parity check matrix of
When the LDPC encoding is performed using the parity check matrix of
As will be described later, the transformed parity check matrix is a matrix represented by a combination of a P×P unit matrix, a quasi unit matrix obtained by setting one or more 1s of the unit matrix to zero (0), a shift matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, a sum matrix serving as a sum of two or more matrices of the unit matrix, the quasi unit matrix, and the shifted matrix, and a P×P zero matrix.
As the transformed parity check matrix is used for decoding of the LDPC code, an architecture of performing P check node operations and P variable node operations at the same time can be employed for decoding the LDPC code as will be described later.
<New LDPC Code>
Incidentally, a terrestrial digital television broadcasting standard called ATSC 3.0 is currently pending.
In this regard, a novel LDPC code which can be used in ATSC 3.0 and other data transmission (hereinafter referred to as a new LDPC code) will be described.
For example, the LDPC code of the DVB scheme or the LDPC code of the ETRI scheme having the unit size P of 360, similarly to DVBT.2 or the like, and corresponding to the parity check matrix having the cyclic structure can be employed as the new LDPC code.
The LDPC encoder 115 (
In this case, the storage unit 602 of the LDPC encoder 115 (
Among the new LDPC codes, the Sony symbol is an LDPC code having particularly excellent performance.
Here, the LDPC code of good performance is an LDPC code obtained from an appropriate parity check matrix H.
The appropriate parity check matrix H is, for example, a parity check matrix that satisfies a predetermined condition to make BER (and FER) smaller when an LDPC code obtained from the parity check matrix H is transmitted at low E_{s}/N_{0 }or E_{b}/N_{o }(signaltonoise power ratio per bit).
For example, the appropriate parity check matrix H can be found by performing simulation to measure BER when LDPC codes obtained from various parity check matrices that satisfy a predetermined condition are transmitted at low E_{s}/N_{o}.
As a predetermined condition to be satisfied by the appropriate parity check matrix H, for example, an analysis result obtained by a code performance analysis method called density evolution (Density Evolution) is excellent, and a loop of elements of 1 does not exist, which is called cycle 4, and so on.
Here, in the information matrix H_{A}, it is known that the decoding performance of LDPC code is deteriorated when elements of 1 are dense like cycle 4, and therefore it is requested that cycle 4 does not exist, as a predetermined condition to be satisfied by the appropriate parity check matrix H.
Here, the predetermined condition to be satisfied by the appropriate parity check matrix H can be arbitrarily determined from the viewpoint of the improvement in the decoding performance of LDPC code and the facilitation (simplification) of decoding processing of LDPC code, and so on.
The density evolution is a code analysis method that calculates the expectation value of the error probability of the entire LDPC code (ensemble) with a code length N of ∞ characterized by a degree sequence described later.
For example, when the dispersion value of noise is gradually increased from 0 on the AWGN channel, the expectation value of the error probability of a certain ensemble is 0 first, but, when the dispersion value of noise becomes equal to or greater than a certain threshold, it is not 0.
According to the density evolution, by comparison of the threshold of the dispersion value of noise (which may also be called a performance threshold) in which the expectation value of the error probability is not 0, it is possible to decide the quality of ensemble performance (appropriateness of the parity check matrix).
Here, as for a specific LDPC code, when an ensemble to which the LDPC code belongs is decided and density evolution is performed for the ensemble, rough performance of the LDPC code can be expected.
Therefore, if an ensemble of good performance is found, an LDPC code of good performance can be found from LDPC codes belonging to the ensemble.
Here, the abovementioned degree sequence shows at what percentage a variable node or check node having the weight of each value exists with respect to the code length N of an LDPC code.
For example, a regular (3,6) LDPC code with an encoding rate of 1/2 belongs to an ensemble characterized by a degree sequence in which the weight (column weight) of all variable nodes is 3 and the weight (row weight) of all check nodes is 6.
In the Tanner graph of
Three branches (edge) equal to the column weight are connected with each variable node, and therefore there are totally 3N branches connected with N variable nodes.
Moreover, six branches (edge) equal to the row weight are connected with each check node, and therefore there are totally 3N branches connected with N/2 check nodes.
In addition, there is one interleaver in the Tanner graph in
The interleaver randomly rearranges 3N branches connected with N variable nodes and connects each rearranged branch with any of IN branches connected with N/2 check nodes.
There are (3N)! (=(3N)×(3N−1)× . . . ×1) rearrangement patterns to rearrange 3N branches connected with N variable nodes in the interleaver. Therefore, an ensemble characterized by the degree sequence in which the weight of all variable nodes is 3 and the weight of all check nodes is 6, becomes aggregation of (3N)! LDPC codes.
In simulation to find an LDPC code of good performance (appropriate parity check matrix), an ensemble of a multiedge type is used in the density evolution.
In the multi edge type, an interleaver through which the branches connected with the variable nodes and the branches connected with the check nodes pass, is divided into plural (multi edge), and, by this means, the ensemble is characterized more strictly.
In the Tanner graph of
Moreover, in the Tanner graph chart of
Furthermore, in the Tanner graph chart of
Here, for example, the density evolution and the mounting thereof are described in “On the Design of LowDensity ParityCheck Codes within 0.0045 dB of the Shannon Limit”, S. Y Chung, G D. Forney, T. J. Richardson, R. Urbanke, IEEE Communications Leggers, VOL.5, NO.2, February 2001.
In simulation to find (a parity check matrix initial value table of) a Sony code, by the density evaluation of the multiedge type, an ensemble in which a performance threshold that is E_{b}/N_{o }(signaltonoise power ratio per bit) with deteriorating (decreasing) BER is equal to or less than a predetermined value is found, and an LDPC code that decreases BER in a case using one or more orthogonal modulations such as QPSK is selected from LDPC codes belonging to the ensemble as an LDPC code of good performance.
The parity check matrix initial value table of the Sony code is found from the abovementioned simulation.
Thus, according to the Sony symbol obtained from the parity check matrix initial value table, it is possible to secure the excellent communication quality in the data transmission.
Every minimum cycle length of the parity check matrices H of the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) has a value exceeding cycle 4, and thus there is no cycle 4 (a loop of 1 elements in which a loop length is 4). Here, the minimum cycle length (girth) is a minimum value of a length (a loop length) of a loop configured with 1 elements in the parity check matrix H.
A performance threshold value of the Sony symbol (16 k, 8/15) is set to 0.805765, a performance threshold value of the Sony symbol (16 k, 10/15) is set to 2.471011, and a performance threshold value of the Sony symbol (16 k, 12/15) is set to 4.269922.
The column weight is set to X1 for KX1 columns of the parity check matrices H of the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=16200 bits) of the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).
In the parity check matrices H of the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
In the parity check matrices H of the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), similarly to the parity check matrix described above with reference to
According to the simulation conducted by the applicant of the present application, an excellent BER/FER is obtained for the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15), and thus it is possible to secure the excellent communication quality in the data transmission using the Sony symbols (16 k, 8/15), (16 k, 10/15), and (16 k, 12/15).
Every minimum cycle length of the parity check matrices H of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) has a value exceeding a cycle 4, and thus there is no cycle 4.
A performance threshold value of the Sony symbol (64 k, 7/15) is set to −0.093751, a performance threshold value of the Sony symbol (64 k, 9/15) is set to 1.658523, a performance threshold value of the Sony symbol (64 k, 11/15) is set to 3.351930, and a performance threshold value of the Sony symbol (64 k, 13/15) is set to 5.301749.
The column weight is set to X1 for KX1 columns of the parity check matrices H of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits) of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).
In the parity check matrices H of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
In the parity check matrices H of the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), similarly to the parity check matrix described above with reference to
According to the simulation conducted by the applicant of the present application, an excellent BER/FER is obtained for the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15), and thus it is possible to secure the excellent communication quality in the data transmission using the Sony symbols (64 k, 7/15), (64 k, 9/15), (64 k, 11/15), and (64 k, 13/15).
The column weight is set to X1 for KX1 columns of the parity check matrices H of the Samsung symbols (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits) of the Samsung symbols (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15).
In the parity check matrices H of the Samsung symbols (64 k, 6/15), (64 k, 8/15), and (64 k, 12/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
The column weight is set to X1 for KX1 columns of the parity check matrices H of the LGE symbols (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=16200 bits) of the LGE symbols (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15).
In the parity check matrices H of the LGE symbols (16 k, 6/15), (16 k, 7/15), (16 k, 9/15), (16 k, 11/15), and (16 k, 13/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
The column weight is set to X1 for KX1 columns of the parity check matrices H of the LGE symbols (64 k, 10/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N(=64800 bits) of the LGE symbols (64 k, 10/15).
In the parity check matrices H of the LGE symbols (64 k, 10/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
The column weight is set to X1 for KX1 columns of the parity check matrices H of the NERC symbols (64 k, 9/15) starting from the 1st column, the column weight is set to X2 for KX2 columns subsequent thereto, the column weight is set to Y1 for KY1 columns subsequent thereto, the column weight is set to Y2 for KY2 columns subsequent thereto, the column weight is set to 2 for M−1 columns subsequent thereto, and the column weight is set to 1 for the last column.
Here, KX1+KX2+KY1+KY2+M−1+1 is equal to the code length N (=64800 bits) of the NERC symbols (64 k, 9/15).
In the parity check matrices H of the NERC symbols (64 k, 9/15), the numbers KX1, KX2, KY1, KY2, and M of columns and column weights X1, X2, Y1, and Y2 are set as illustrated in
For the parity check matrix H of the ETRI symbol (16 k, 5/15), the parameter g=M_{1 }is 720.
Further, for the ETRI symbol (16 k, 5/15), since the code length N is 16200 and the encoding rate r is 5/15, the information length K=N×r is 16200×5/15=5400 and the parity length M=N−K is 16200−5400=10800.
Further, the parameter M_{2}=M−M_{1}=N−K−g is 10800−720=10080.
Thus, the parameter Q_{1}=M_{1}/P is 720/360=2, and the parameter Q_{2}=M_{2}/P is 10080/360=28.
For the parity check matrices H of the ETRI symbols of (64 k, 5/15), (64 k, 6/15), and (64 k, 7/15), the parameters g=M_{1}, M_{2}, Q_{1}, and Q_{2 }are set as illustrated in
<Constellation>
In the transmission system of
In other words, in the transmission system of
Further, in the transmission system of
The constellations include uniform constellations (UCs) in which an arrangement of signal points is uniform, and non uniform constellations (NUCs) in which an arrangement of signal points is not uniform.
Examples of NUCs include a constellation called a 1dimensional M^{2}QAM nonuniform constellation (1D NUC) and a constellation called a 2dimensional QQAM nonuniform constellation (2D NUC).
Commonly, the 1D NUC is better in the BER than the UC, and the 2D NUC is better in the BER than the 1D NUC.
A constellation in which the modulation scheme is QPSK is the UC. For example, the 2D NUC can be employed as the constellation in which the modulation scheme is 16QAM, 64QAM, 256QAM, or the like, and for example, the 1D NUC can be employed as the constellation in which the modulation scheme is 1024QAM, 4096QAM, or the like.
Hereinafter, a constellation of an NUC used in MODCOD in which the modulation scheme is a modulation scheme in which an mbit symbol is mapped to any of 2^{m }signal points, and an encoding rate of an LDPC is r is also referred to as NUC r.
For example, “NUC_16_6/15” indicates a constellation of an NUC used in MODCOD in which the modulation scheme is 16QAM (or the modulation scheme in which a symbol is mapped to any of 16 signal points), and the encoding rate r of the LDPC code is 6/15.
In the transmission system of
Further, in the transmission system of
Further, in the transmission system of
Thus, as described above, when the LDPC codes are classified into the 9 types of LDPC codes of r=5/15, 6/15, 7/15, 8/15, 9/15, 10/15, 11/15, 12, 15, 13/15 according to the encoding rate r, one type of constellation is prepared for QPSK, 9 types of constellations of a 2D NUC are prepared for each of 16QAM, 64QAM, and 256QAM, and 9 types of constellations of a 1D NUC are prepared for each of 1024QAM and 4096QAM.
In
In
In
In
In
In
In
In the 2D NUC, a signal point of a second quadrant of the constellation is arranged at a position to which the signal point of the first quadrant has moved symmetrically to the Q axis, and a signal point of a third quadrant of the constellation is arranged at a position to which the signal point of the first quadrant has moved symmetrically to an origin. Further, a signal point of a fourth quadrant of the constellation is arranged at a position to which the signal point of the first quadrant has moved symmetrically to the I axis.
Here, when the modulation scheme is 2^{m}QAM, m bits are used as one symbol, and one symbol is mapped to a signal point corresponding to the symbol.
The mbit symbol is expressed by, for example, an integer value of 0 to 2^{m}−1, but if b=2^{m}/4 is assumed, symbols y(0), y(1), . . . , and y(2^{m}−1) expressed by the integer value of 0 to 2^{m}−1 can be classified into four symbols y(0) to y(b−1), y(b) to y(2b−1), y(2b) to y(3b−1), and y(3b) to y(4b−1).
In
Further, coordinates of a signal point corresponding to the symbol y(k+b) within the range of the symbols y(b) to y(2b−1) are indicated by −conj(w#k), and coordinates of a signal point corresponding to the symbol y(k+2b) within the range of the symbols y(2b) to y(3b−1) are indicated by conj(w#k). Further, coordinates of a signal point corresponding to the symbol y(k+3b) within the range of the symbols y(3b) to y(4b−1) are indicated by −w#k.
Here, conj(w#k) indicates a complex conjugate of w#k.
For example, when the modulation scheme is 16QAM, the symbols y(0), y(1), . . . , and y(15) of m=4 bits are classified into four symbols y(0) to y(3), y(4) to y(7), y(8) to y(11), and y(12) to y(15) if b=2^{4}/4=4.
Among the symbols y(0) to y(15), for example, the symbol y(12) is the symbol y(k+3b)=y(0+3×4) within the symbols y(3b) to y(4b−1), and k is zero (0), and thus the coordinates of the signal point corresponding to the symbol y(12) are −w#k=−w0.
Now, for example, if the encoding rate r of the LDPC code is 9/15, according to
In
u#k indicates the real part Re(z_{q}) and the imaginary part Im(z_{q}) of the complex number serving as the coordinates of the signal point z_{q }of the 1D NUC.
Now, the 10bit symbol y of 1024QAM is assumed to be indicated by y_{0,q}, y_{1,q}, y_{2,q}, y_{3,q}, y_{4,q}, y_{5,q}, y_{6,q}, y_{7,q}, y_{8,q}, and y_{9,q }from the first bit (the most significant bit).
A of
B of
For example, when the 10bit symbol y=(y_{0,q}, y_{1,q}, y_{2,q}, y_{3,q}, y_{4,q}, y_{5,q}, y_{6,q}, y_{7,q}, y_{8,q}, y_{9,q}) of 1024QAM is (0, 0, 1, 0, 0, 1, 1, 1, 0, 0), the 5 oddnumbered bits (y_{0,q}, y_{2,q}, y_{4,q}, y_{6,q}, y_{8,q}) are (0, 1, 0, 1, 0), and the 5 evennumbered bits (y_{1,q}, y_{3,q}, y_{5,q}, y_{7,q}, and y_{9,q}) are (0, 0, 1, 1, 0).
In A of
In B of
Meanwhile, for example, if the encoding rate r of the LDPC code is 7/15, according to
Thus, the real part Re(z_{q}) of the signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) is u3 (=1.1963), and Im(z_{q}) is u11 (=6.9391). As a result, the coordinates of the signal point z_{q }corresponding to the symbol y=(0, 0, 1, 0, 0, 1, 1, 1, 0, 0) are indicated by 1.1963+6.9391i.
In
u#k indicates the real part Re(z_{q}) and the imaginary part Im(z_{q}) of the complex number serving as the coordinates of the signal point z_{q }of the 1D NUC.
A method of obtaining the coordinates of the signal point of the 1D NUC of 4096QAM using
In
In
The signal points of the 1D NUC are arranged in a grid form on a straight line parallel to the I axis or a straight line parallel to the Q axis. However, an interval between the signal points is not constant. Further, when the signal point (the mapped data) is transmitted, average power of the signal points on the constellation is normalized. The normalization is performed by multiplying each signal point z_{q }on the constellation by a reciprocal 1/(√P_{ave}) of a square root √P_{ave }of a root mean square value P_{ave }when a root mean square value of an absolute value for (coordinates of) all signal points on the constellation is indicated by P_{ave}.
According to the constellations described above with reference to
<Block Interleaver 25>
The block interleaver 25 includes a storage region called a part 1 and a storage region called a part 2.
Each of the parts 1 and 2 is configured such that a number C of columns equal in number to the number m of bits of the symbol and serving as storage regions that store one bit in the row (horizontal) direction and store a predetermined number of bits in the column (vertical) direction are arranged.
If the number of bits (hereinafter, also referred to as a part column length) that are stored in the column direction by the column of the part 1 is indicated by R1, and the part column length of the column of the part 2 is indicated by R2, (R1+R2)×C is equal to the code length N (64800 bits or 16200 bits in the present embodiment) of the LDPC code of the block interleave target.
Further, the part column length R1 is equal to a multiple of 360 bits serving as the unit size P, and the part column length R2 is equal to a remainder when a sum (hereinafter, also referred to as a column length) R1+R2 of the part column length R1 of the part 1 and the part column length R2 of the part 2 is divided by 360 bits serving as the unit size P.
Here, the column length R1+R2 is equal to a value obtained by dividing the code length N of the LDPC code of the block interleave target by the number m of bits of the symbol.
For example, when 16QAM is employed as the modulation scheme for the LDPC code in which the code length N is 16200 bits, the number m of bits of the symbol is 4 bits, and thus the column length R1+R2 is 4050 (=16200/4) bits.
Further, since the remainder when the column length R1+R2=4050 is divided by 360 bits serving as the unit size P is 90, the part column length R2 of the part 2 is 90 bits.
Further, the part column length R1 of the part 1 is R1+R2−R2=405090=3960 bits.
The block interleaver 25 performs the block interleave by writing the LDPC code in the parts 1 and 2 and reading the LDPC code from the parts 1 and 2.
In other words, in the block interleave, writing of the code bits of the LDPC code of one code word downward (in the column direction) in the column of the part 1 is performed from the column at the left side to the column at the right side as illustrated in A of
Then, when the writing of the code bits is completed to the bottom of the rightmost column (a Cth column) of the columns of the part 1, writing of the remaining code bits downward (in the column direction) in the column of the part 2 is performed from the column at the left side to the column at the right side.
Thereafter, when the writing of the code bits is completed to the bottom of the rightmost column (the Cth column) of the columns of the part 2, the code bits are read from the 1st rows of all the C columns of the part 1 in the row direction in units of C=m bits.
Then, the reading of the code bits from all the C columns of the part 1 is sequentially performed toward a row therebelow, and when the reading is completed up to an R1th row serving as the last row, the code bits are read from the 1st rows of all the C columns of the part 2 in the row direction in units of C=m bits.
The reading of the code bits from all the C columns of the part 2 is sequentially performed toward a row therebelow and the reading is performed up to an R2 row serving as the last row.
As a result, the code bits read from the parts 1 and 2 in units of m bits are supplied to the mapper 117 (
<GroupWise Interleave>
In the groupwise interleave, 360 bits of one segment are used as the bit group, where the LDPC code of one code word is divided into segments in units of 360 bits equal to the unit size P, and the LDPC code of one code word is interleaved according to a predetermined pattern (hereinafter, also referred to as a GW pattern), starting from the head.
Here, when the LDPC code of one code word is segmented into the bit groups, an (i+1)th bit group from the head is also referred to as a bit group i.
When the unit size P is 360, for example, the LDPC code in which the code length N is 1800 bits is segmented into bit groups 0, 1, 2, 3, and 4, that is, 5 (=1800/360) bit groups. Further, for example, the LDPC code in which the code length N is 16200 bits is segmented into bit groups 0, 1, . . . , and 44, that is, 45 (=16200/360) bit groups, and the LDPC code in which the code length N is 64800 bits is segmented into bit groups 0, 1, . . . , and 179, that is, 180 (=64800/360) bit groups.
Hereinafter, the GW pattern is assumed to be indicated by a sequence of numbers indicating a bit group. For example, for the LDPC code in which the code length N is 1800 bits, for example, the GW pattern 4, 2, 0, 3, 1 indicates that a sequence of bit groups 0, 1, 2, 3, and 4 is interleaved (rearranged) into a sequence of bit groups 4, 2, 0, 3, and 1.
The GW pattern can be set at least for each code length N of the LDPC code.
<Example of GW Pattern for LDPC Code of 64 Kbits>
According to the GW pattern of
39, 47, 96, 176, 33, 75, 165, 38, 27, 58, 90, 76, 17, 46, 10, 91, 133, 69, 171, 32, 117, 78, 13, 146, 101, 36, 0, 138, 25, 77, 122, 49, 14, 125, 140, 93, 130, 2, 104, 102, 128, 4, 111, 151, 84, 167, 35, 127, 156, 55, 82, 85, 66, 114, 8, 147, 115, 113, 5, 31, 100, 106, 48, 52, 67, 107, 18, 126, 112, 50, 9, 143, 28, 160, 71, 79, 43, 98, 86, 94, 64, 3, 166, 105, 103, 118, 63, 51, 139, 172, 141, 175, 56, 74, 95, 29, 45, 129, 120, 168, 92, 150, 7, 162, 153, 137, 108, 159, 157, 173, 23, 89, 132, 57, 37, 70, 134, 40, 21, 149, 80, 1, 121, 59, 110, 142, 152, 15, 154, 145, 12, 170, 54, 155, 99, 22, 123, 72, 177, 131, 116, 44, 158, 73, 11, 65, 164, 119, 174, 34, 83, 53, 24, 42, 60, 26, 161, 68, 178, 41, 148, 109, 87, 144, 135, 20, 62, 81, 169, 124, 6, 19, 30, 163, 61, 179, 136, 97, 16, and 88.
According to the GW pattern of
6, 14, 1, 127, 161, 177, 75, 123, 62, 103, 17, 18, 167, 88, 27, 34, 8, 110, 7, 78, 94, 44, 45, 166, 149, 61, 163, 145, 155, 157, 82, 130, 70, 92, 151, 139, 160, 133, 26, 2, 79, 15, 95, 122, 126, 178, 101, 24, 138, 146, 179, 30, 86, 58, 11, 121, 159, 49, 84, 132, 117, 119, 50, 52, 4, 51, 48, 74, 114, 59, 40, 131, 33, 89, 66, 136, 72, 16, 134, 37, 164, 77, 99, 173, 20, 158, 156, 90, 41, 176, 81, 42, 60, 109, 22, 150, 105, 120, 12, 64, 56, 68, 111, 21, 148, 53, 169, 97, 108, 35, 140, 91, 115, 152, 36, 106, 154, 0, 25, 54, 63, 172, 80, 168, 142, 118, 162, 135, 73, 83, 153, 141, 9, 28, 55, 31, 112, 107, 85, 100, 175, 23, 57, 47, 38, 170, 137, 76, 147, 93, 19, 98, 124, 39, 87, 174, 144, 46, 10, 129, 69, 71, 125, 96, 116, 171, 128, 65, 102, 5, 43, 143, 104, 13, 67, 29, 3, 113, 32, and 165.
According to the GW pattern of
103, 116, 158, 0, 27, 73, 140, 30, 148, 36, 153, 154, 10, 174, 122, 178, 6, 106, 162, 59, 142, 112, 7, 74, 11, 51, 49, 72, 31, 65, 156, 95, 171, 105, 173, 168, 1, 155, 125, 82, 86, 161, 57, 165, 54, 26, 121, 25, 157, 93, 22, 34, 33, 39, 19, 46, 150, 141, 12, 9, 79, 118, 24, 17, 85, 117, 67, 58, 129, 160, 89, 61, 146, 77, 130, 102, 101, 137, 94, 69, 14, 133, 60, 149, 136, 16, 108, 41, 90, 28, 144, 13, 175, 114, 2, 18, 63, 68, 21, 109, 53, 123, 75, 81, 143, 169, 42, 119, 138, 104, 4, 131, 145, 8, 5, 76, 15, 88, 177, 124, 45, 97, 64, 100, 37, 132, 38, 44, 107, 35, 43, 80, 50, 91, 152, 78, 166, 55, 115, 170, 159, 147, 167, 87, 83, 29, 96, 172, 48, 98, 62, 139, 70, 164, 84, 47, 151, 134, 126, 113, 179, 110, 111, 128, 32, 52, 66, 40, 135, 176, 99, 127, 163, 3, 120, 71, 56, 92, 23, and 20.
According to the GW pattern of
139, 106, 125, 81, 88, 104, 3, 66, 60, 65, 2, 95, 155, 24, 151, 5, 51, 53, 29, 75, 52, 85, 8, 22, 98, 93, 168, 15, 86, 126, 173, 100, 130, 176, 20, 10, 87, 92, 175, 36, 143, 110, 67, 146, 149, 127, 133, 42, 84, 64, 78, 1, 48, 159, 79, 138, 46, 112, 164, 31, 152, 57, 144, 69, 27, 136, 122, 170, 132, 171, 129, 115, 107, 134, 89, 157, 113, 119, 135, 45, 148, 83, 114, 71, 128, 161, 140, 26, 13, 59, 38, 35, 96, 28, 0, 80, 174, 137, 49, 16, 101, 74, 179, 91, 44, 55, 169, 131, 163, 123, 145, 162, 108, 178, 12, 77, 167, 21, 154, 82, 54, 90, 177, 17, 41, 39, 7, 102, 156, 62, 109, 14, 37, 23, 153, 6, 147, 50, 47, 63, 18, 70, 68, 124, 72, 33, 158, 32, 118, 99, 105, 94, 25, 121, 166, 120, 160, 141, 165, 111, 19, 150, 97, 76, 73, 142, 117, 4, 172, 58, 11, 30, 9, 103, 40, 61, 43, 34, 56, and 116.
According to the GW pattern of
72, 59, 65, 61, 80, 2, 66, 23, 69, 101, 19, 16, 53, 109, 74, 106, 113, 56, 97, 30, 164, 15, 25, 20, 117, 76, 50, 82, 178, 13, 169, 36, 107, 40, 122, 138, 42, 96, 27, 163, 46, 64, 124, 57, 87, 120, 168, 166, 39, 177, 22, 67, 134, 9, 102, 28, 148, 91, 83, 88, 167, 32, 99, 140, 60, 152, 1, 123, 29, 154, 26, 70, 149, 171, 12, 6, 55, 100, 62, 86, 114, 174, 132, 139, 7, 45, 103, 130, 31, 49, 151, 119, 79, 41, 118, 126, 3, 179, 110, 111, 51, 93, 145, 73, 133, 54, 104, 161, 37, 129, 63, 38, 95, 159, 89, 112, 115, 136, 33, 68, 17, 35, 137, 173, 143, 78, 77, 141, 150, 58, 158, 125, 156, 24, 105, 98, 43, 84, 92, 128, 165, 153, 108, 0, 121, 170, 131, 144, 47, 157, 11, 155, 176, 48, 135, 4, 116, 146, 127, 52, 162, 142, 8, 5, 34, 85, 90, 44, 172, 94, 160, 175, 75, 71, 18, 147, 10, 21, 14, and 81.
According to the GW pattern of
8, 27, 7, 70, 75, 84, 50, 131, 146, 99, 96, 141, 155, 157, 82, 57, 120, 38, 137, 13, 83, 23, 40, 9, 56, 171, 124, 172, 39, 142, 20, 128, 133, 2, 89, 153, 103, 112, 129, 151, 162, 106, 14, 62, 107, 110, 73, 71, 177, 154, 80, 176, 24, 91, 32, 173, 25, 16, 17, 159, 21, 92, 6, 67, 81, 37, 15, 136, 100, 64, 102, 163, 168, 18, 78, 76, 45, 140, 123, 118, 58, 122, 11, 19, 86, 98, 119, 111, 26, 138, 125, 74, 97, 63, 10, 152, 161, 175, 87, 52, 60, 22, 79, 104, 30, 158, 54, 145, 49, 34, 166, 109, 179, 174, 93, 41, 116, 48, 3, 29, 134, 167, 105, 132, 114, 169, 147, 144, 77, 61, 170, 90, 178, 0, 43, 149, 130, 117, 47, 44, 36, 115, 88, 101, 148, 69, 46, 94, 143, 164, 139, 126, 160, 156, 33, 113, 65, 121, 53, 42, 66, 165, 85, 127, 135, 5, 55, 150, 72, 35, 31, 51, 4, 1, 68, 12, 28, 95, 59, and 108.
According to the GW pattern of
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177, and 179.
According to the GW pattern of
11, 5, 8, 18, 1, 25, 32, 31, 19, 21, 50, 102, 65, 85, 45, 86, 98, 104, 64, 78, 72, 53, 103, 79, 93, 41, 82, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 4, 12, 15, 3, 10, 20, 26, 34, 23, 33, 68, 63, 69, 92, 44, 90, 75, 56, 100, 47, 106, 42, 39, 97, 99, 89, 52, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 6, 16, 14, 7, 13, 36, 28, 29, 37, 73, 70, 54, 76, 91, 66, 80, 88, 51, 96, 81, 95, 38, 57, 105, 107, 59, 61, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 0, 9, 17, 2, 27, 30, 24, 22, 35, 77, 74, 46, 94, 62, 87, 83, 101, 49, 43, 84, 48, 60, 67, 71, 58, 40, 55, 111, 115, 119, 123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, and 179.
According to the GW pattern of
9, 18, 15, 13, 35, 26, 28, 99, 40, 68, 85, 58, 63, 104, 50, 52, 94, 69, 108, 114, 120, 126, 132, 138, 144, 150, 156, 162, 168, 174, 8, 16, 17, 24, 37, 23, 22, 103, 64, 43, 47, 56, 92, 59, 70, 42, 106, 60, 109, 115, 121, 127, 133, 139, 145, 151, 157, 163, 169, 175, 4, 1, 10, 19, 30, 31, 89, 86, 77, 81, 51, 79, 83, 48, 45, 62, 67, 65, 110, 116, 122, 128, 134, 140, 146, 152, 158, 164, 170, 176, 6, 2, 0, 25, 20, 34, 98, 105, 82, 96, 90, 107, 53, 74, 73, 93, 55, 102, 111, 117, 123, 129, 135, 141, 147, 153, 159, 165, 171, 177, 14, 7, 3, 27, 21, 33, 44, 97, 38, 75, 72, 41, 84, 80, 100, 87, 76, 57, 112, 118, 124, 130, 136, 142, 148, 154, 160, 166, 172, 178, 5, 11, 12, 32, 29, 36, 88, 71, 78, 95, 49, 54, 61, 66, 46, 39, 101, 91, 113, 119, 125, 131, 137, 143, 149, 155, 161, 167, 173, and 179.
According to the GW pattern of
0, 14, 19, 21, 2, 11, 22, 9, 8, 7, 16, 3, 26, 24, 27, 80, 100, 121, 107, 31, 36, 42, 46, 49, 75, 93, 127, 95, 119, 73, 61, 63, 117, 89, 99, 129, 52, 111, 124, 48, 122, 82, 106, 91, 92, 71, 103, 102, 81, 113, 101, 97, 33, 115, 59, 112, 90, 51, 126, 85, 123, 40, 83, 53, 69, 70, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 4, 5, 10, 12, 20, 6, 18, 13, 17, 15, 1, 29, 28, 23, 25, 67, 116, 66, 104, 44, 50, 47, 84, 76, 65, 130, 56, 128, 77, 39, 94, 87, 120, 62, 88, 74, 35, 110, 131, 98, 60, 37, 45, 78, 125, 41, 34, 118, 38, 72, 108, 58, 43, 109, 57, 105, 68, 86, 79, 96, 32, 114, 64, 55, 30, 54, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177, and 179.
According to the GW pattern of
21, 11, 12, 9, 0, 6, 24, 25, 85, 103, 118, 122, 71, 101, 41, 93, 55, 73, 100, 40, 106, 119, 45, 80, 128, 68, 129, 61, 124, 36, 126, 117, 114, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 20, 18, 10, 13, 16, 8, 26, 27, 54, 111, 52, 44, 87, 113, 115, 58, 116, 49, 77, 95, 86, 30, 78, 81, 56, 125, 53, 89, 94, 50, 123, 65, 83, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 2, 17, 1, 4, 7, 15, 29, 82, 32, 102, 76, 121, 92, 130, 127, 62, 107, 38, 46, 43, 110, 75, 104, 70, 91, 69, 96, 120, 42, 34, 79, 35, 105, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 19, 5, 3, 14, 22, 28, 23, 109, 51, 108, 131, 33, 84, 88, 64, 63, 59, 57, 97, 98, 48, 31, 99, 37, 72, 39, 74, 66, 60, 67, 47, 112, 90, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, and 179.
According to the GW pattern of
12, 15, 2, 16, 27, 50, 35, 74, 38, 70, 108, 32, 112, 54, 30, 122, 72, 116, 36, 90, 49, 85, 132, 138, 144, 150, 156, 162, 168, 174, 0, 14, 9, 5, 23, 66, 68, 52, 96, 117, 84, 128, 100, 63, 60, 127, 81, 99, 53, 55, 103, 95, 133, 139, 145, 151, 157, 163, 169, 175, 10, 22, 13, 11, 28, 104, 37, 57, 115, 46, 65, 129, 107, 75, 119, 110, 31, 43, 97, 78, 125, 58, 134, 140, 146, 152, 158, 164, 170, 176, 4, 19, 6, 8, 24, 44, 101, 94, 118, 130, 69, 71, 83, 34, 86, 124, 48, 106, 89, 40, 102, 91, 135, 141, 147, 153, 159, 165, 171, 177, 3, 20, 7, 17, 25, 87, 41, 120, 47, 80, 59, 62, 88, 45, 56, 131, 61, 126, 113, 92, 51, 98, 136, 142, 148, 154, 160, 166, 172, 178, 21, 18, 1, 26, 29, 39, 73, 121, 105, 77, 42, 114, 93, 82, 111, 109, 67, 79, 123, 64, 76, 33, 137, 143, 149, 155, 161, 167, 173, and 179.
According to the GW pattern of
0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 66, 68, 70, 72, 74, 76, 78, 80, 82, 84, 86, 88, 90, 92, 94, 96, 98, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176, 178, 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127, 129, 131, 133, 135, 137, 139, 141, 143, 145, 147, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 169, 171, 173, 175, 177, and 179.
According to the GW pattern of
0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69, 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129, 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74, 78, 82, 86, 90, 94, 98, 102, 106, 110, 114, 118, 122, 126, 130, 134, 138, 142, 146, 150, 154, 158, 162, 166, 170, 174, 178, 3, 7, 11, 15, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 75, 79, 83, 87, 91, 95, 99, 103, 107, 111, 115, 119, 123, 127, 131, 135, 139, 143, 147, 151, 155, 159, 163, 167, 171, 175, and 179.
According to the GW pattern of
8, 112, 92, 165, 12, 55, 5, 126, 87, 70, 69, 94, 103, 78, 137, 148, 9, 60, 13, 7, 178, 79, 43, 136, 34, 68, 118, 152, 49, 15, 99, 61, 66, 28, 109, 125, 33, 167, 81, 93, 97, 26, 35, 30, 153, 131, 122, 71, 107, 130, 76, 4, 95, 42, 58, 134, 0, 89, 75, 40, 129, 31, 80, 101, 52, 16, 142, 44, 138, 46, 116, 27, 82, 88, 143, 128, 72, 29, 83, 117, 172, 14, 51, 159, 48, 160, 100, 1, 102, 90, 22, 3, 114, 19, 108, 113, 39, 73, 111, 155, 106, 105, 91, 150, 54, 25, 135, 139, 147, 36, 56, 123, 6, 67, 104, 96, 157, 10, 62, 164, 86, 74, 133, 120, 174, 53, 140, 156, 171, 149, 127, 85, 59, 124, 84, 11, 21, 132, 41, 145, 158, 32, 17, 23, 50, 169, 170, 38, 18, 151, 24, 166, 175, 2, 47, 57, 98, 20, 177, 161, 154, 176, 163, 37, 110, 168, 141, 64, 65, 173, 162, 121, 45, 77, 115, 179, 63, 119, 146, and 144.
According to the GW pattern of
103, 138, 168, 82, 116, 45, 178, 28, 160, 2, 129, 148, 150, 23, 54, 106, 24, 78, 49, 87, 145, 179, 26, 112, 119, 12, 18, 174, 21, 48, 134, 137, 102, 147, 152, 72, 68, 3, 22, 169, 30, 64, 108, 142, 131, 13, 113, 115, 121, 37, 133, 136, 101, 59, 73, 161, 38, 164, 43, 167, 42, 144, 41, 85, 91, 58, 128, 154, 172, 57, 75, 17, 157, 19, 4, 86, 15, 25, 35, 9, 105, 123, 14, 34, 56, 111, 60, 90, 74, 149, 146, 62, 163, 31, 16, 141, 88, 6, 155, 130, 89, 107, 135, 79, 8, 10, 124, 171, 114, 162, 33, 66, 126, 71, 44, 158, 51, 84, 165, 173, 120, 7, 11, 170, 176, 1, 156, 96, 175, 153, 36, 47, 110, 63, 132, 29, 95, 143, 98, 70, 20, 122, 53, 100, 93, 140, 109, 139, 76, 151, 52, 61, 46, 125, 94, 50, 67, 81, 69, 65, 40, 127, 77, 32, 39, 27, 99, 97, 159, 166, 80, 117, 55, 92, 118, 0, 5, 83, 177, and 104.
According to the GW pattern of
104, 120, 47, 136, 116, 109, 22, 20, 117, 61, 52, 108, 86, 99, 76, 90, 37, 58, 36, 138, 95, 130, 177, 93, 56, 33, 24, 82, 0, 67, 83, 46, 79, 70, 154, 18, 75, 43, 49, 63, 162, 16, 167, 80, 125, 1, 123, 107, 9, 45, 53, 15, 38, 23, 57, 141, 4, 178, 165, 113, 21, 105, 11, 124, 126, 77, 146, 29, 131, 27, 176, 40, 74, 91, 140, 64, 73, 44, 129, 157, 172, 51, 10, 128, 119, 163, 103, 28, 85, 156, 78, 6, 8, 173, 160, 106, 31, 54, 122, 25, 139, 68, 150, 164, 87, 135, 97, 166, 42, 169, 161, 137, 26, 39, 133, 5, 94, 69, 2, 30, 171, 149, 115, 96, 145, 101, 92, 143, 12, 88, 81, 71, 19, 147, 50, 152, 159, 155, 151, 174, 60, 32, 3, 142, 72, 14, 170, 112, 65, 89, 175, 158, 17, 114, 62, 144, 13, 98, 66, 59, 7, 118, 48, 153, 100, 134, 84, 111, 132, 127, 41, 168, 110, 102, 34, 121, 179, 148, 55, and 35.
According to the GW pattern of
37, 98, 160, 63, 18, 6, 94, 136, 8, 50, 0, 75, 65, 32, 107, 60, 108, 17, 21, 156, 157, 5, 73, 66, 38, 177, 162, 130, 171, 76, 57, 126, 103, 62, 120, 134, 154, 101, 143, 29, 13, 149, 16, 33, 55, 56, 159, 128, 23, 146, 153, 141, 169, 49, 46, 152, 89, 155, 111, 127, 48, 14, 93, 41, 7, 78, 135, 69, 123, 179, 36, 87, 27, 58, 88, 170, 125, 110, 15, 97, 178, 90, 121, 173, 30, 102, 10, 80, 104, 166, 64, 4, 147, 1, 52, 45, 148, 68, 158, 31, 140, 100, 85, 115, 151, 70, 39, 82, 122, 79, 12, 91, 133, 132, 22, 163, 47, 19, 119, 144, 35, 25, 42, 83, 92, 26, 72, 138, 54, 124, 24, 74, 118, 117, 168, 71, 109, 112, 106, 176, 175, 44, 145, 11, 9, 161, 96, 77, 174, 137, 34, 84, 2, 164, 129, 43, 150, 61, 53, 20, 165, 113, 142, 116, 95, 3, 28, 40, 81, 99, 139, 114, 59, 67, 172, 131, 105, 167, 51, and 86.
According to the GW pattern of
58, 70, 23, 32, 26, 63, 55, 48, 35, 41, 53, 20, 38, 51, 61, 65, 44, 29, 7, 2, 113, 68, 96, 104, 106, 89, 27, 0, 119, 21, 4, 49, 46, 100, 13, 36, 57, 98, 102, 9, 42, 39, 33, 62, 22, 95, 101, 15, 91, 25, 93, 132, 69, 87, 47, 59, 67, 124, 17, 11, 31, 43, 40, 37, 85, 50, 97, 140, 45, 92, 56, 30, 34, 60, 107, 24, 52, 94, 64, 5, 71, 90, 66, 103, 88, 86, 84, 19, 169, 159, 147, 126, 28, 130, 14, 162, 144, 166, 108, 153, 115, 135, 120, 122, 112, 139, 151, 156, 16, 172, 164, 123, 99, 54, 136, 81, 105, 128, 116, 150, 155, 76, 18, 142, 170, 175, 83, 146, 78, 109, 73, 131, 127, 82, 167, 77, 110, 79, 137, 152, 3, 173, 148, 72, 158, 117, 1, 6, 12, 8, 161, 74, 143, 133, 168, 171, 134, 163, 138, 121, 141, 160, 111, 10, 149, 80, 75, 165, 157, 174, 129, 145, 114, 125, 154, 118, 176, 177, 178, and 179.
According to the GW pattern of
40, 159, 100, 14, 88, 75, 53, 24, 157, 84, 23, 77, 140, 145, 32, 28, 112, 39, 76, 50, 93, 27, 107, 25, 152, 101, 127, 5, 129, 71, 9, 21, 96, 73, 35, 106, 158, 49, 136, 30, 137, 115, 139, 48, 167, 85, 74, 72, 7, 110, 161, 41, 170, 147, 82, 128, 149, 33, 8, 120, 47, 68, 58, 67, 87, 155, 11, 18, 103, 151, 29, 36, 83, 135, 79, 150, 97, 54, 70, 138, 156, 31, 121, 34, 20, 130, 61, 57, 2, 166, 117, 15, 6, 165, 118, 98, 116, 131, 109, 62, 126, 175, 22, 111, 164, 16, 133, 102, 55, 105, 64, 177, 78, 37, 162, 124, 119, 19, 4, 69, 132, 65, 123, 160, 17, 52, 38, 1, 80, 90, 42, 81, 104, 13, 144, 51, 114, 3, 43, 146, 163, 59, 45, 89, 122, 169, 44, 94, 86, 99, 66, 171, 173, 0, 141, 148, 176, 26, 143, 178, 60, 153, 142, 91, 179, 12, 168, 113, 95, 174, 56, 134, 92, 46, 108, 125, 10, 172, 154, and 63.
According to the GW pattern of
143, 57, 67, 26, 134, 112, 136, 103, 13, 94, 16, 116, 169, 95, 98, 6, 174, 173, 102, 15, 114, 39, 127, 78, 18, 123, 121, 4, 89, 115, 24, 108, 74, 63, 175, 82, 48, 20, 104, 92, 27, 3, 33, 106, 62, 148, 154, 25, 129, 69, 178, 156, 87, 83, 100, 122, 70, 93, 50, 140, 43, 125, 166, 41, 128, 85, 157, 49, 86, 66, 79, 130, 133, 171, 21, 165, 126, 51, 153, 38, 142, 109, 10, 65, 23, 91, 90, 73, 61, 42, 47, 131, 77, 9, 58, 96, 101, 37, 7, 159, 44, 2, 170, 160, 162, 0, 137, 31, 45, 110, 144, 88, 8, 11, 40, 81, 168, 135, 56, 151, 107, 105, 32, 120, 132, 1, 84, 161, 179, 72, 176, 71, 145, 139, 75, 141, 97, 17, 149, 124, 80, 60, 36, 52, 164, 53, 158, 113, 34, 76, 5, 111, 155, 138, 19, 35, 167, 172, 14, 147, 55, 152, 59, 64, 54, 117, 146, 118, 119, 150, 29, 163, 68, 99, 46, 177, 28, 22, 30, and 12.
According to the GW pattern of
116, 47, 155, 89, 109, 137, 103, 60, 114, 14, 148, 100, 28, 132, 129, 105, 154, 7, 167, 140, 160, 30, 57, 32, 81, 3, 86, 45, 69, 147, 125, 52, 20, 22, 156, 168, 17, 5, 93, 53, 61, 149, 56, 62, 112, 48, 11, 21, 166, 73, 158, 104, 79, 128, 135, 126, 63, 26, 44, 97, 13, 151, 123, 41, 118, 35, 131, 8, 90, 58, 134, 6, 78, 130, 82, 106, 99, 178, 102, 29, 108, 120, 107, 139, 23, 85, 36, 172, 174, 138, 95, 145, 170, 122, 50, 19, 91, 67, 101, 92, 179, 27, 94, 66, 171, 39, 68, 9, 59, 146, 15, 31, 38, 49, 37, 64, 77, 152, 144, 72, 165, 163, 24, 1, 2, 111, 80, 124, 43, 136, 127, 153, 75, 42, 113, 18, 164, 133, 142, 98, 96, 4, 51, 150, 46, 121, 76, 10, 25, 176, 34, 110, 115, 143, 173, 169, 40, 65, 157, 175, 70, 33, 141, 71, 119, 16, 162, 177, 12, 84, 87, 117, 0, 88, 161, 55, 54, 83, 74, and 159.
According to the GW pattern of
62, 17, 10, 25, 174, 13, 159, 14, 108, 0, 42, 57, 78, 67, 41, 132, 110, 87, 77, 27, 88, 56, 8, 161, 7, 164, 171, 44, 75, 176, 145, 165, 157, 34, 142, 98, 103, 52, 11, 82, 141, 116, 15, 158, 139, 120, 36, 61, 20, 112, 144, 53, 128, 24, 96, 122, 114, 104, 150, 50, 51, 80, 109, 33, 5, 95, 59, 16, 134, 105, 111, 21, 40, 146, 18, 133, 60, 23, 160, 106, 32, 79, 55, 6, 1, 154, 117, 19, 152, 167, 166, 30, 35, 100, 74, 131, 99, 156, 39, 76, 86, 43, 178, 155, 179, 177, 136, 175, 81, 64, 124, 153, 84, 163, 135, 115, 125, 47, 45, 143, 72, 48, 172, 97, 85, 107, 126, 91, 129, 137, 83, 118, 54, 2, 9, 58, 169, 73, 123, 4, 92, 168, 162, 94, 138, 119, 22, 31, 63, 89, 90, 69, 49, 173, 28, 127, 26, 29, 101, 170, 93, 140, 147, 149, 148, 66, 65, 121, 12, 71, 37, 70, 102, 46, 38, 68, 130, 3, 113, and 151.
According to the GW pattern of
168, 18, 46, 131, 88, 90, 11, 89, 111, 174, 172, 38, 78, 153, 9, 80, 53, 27, 44, 79, 35, 83, 171, 51, 37, 99, 95, 119, 117, 127, 112, 166, 28, 123, 33, 160, 29, 6, 135, 10, 66, 69, 74, 92, 15, 109, 106, 178, 65, 141, 0, 3, 154, 156, 164, 7, 45, 115, 122, 148, 110, 24, 121, 126, 23, 175, 21, 113, 58, 43, 26, 143, 56, 142, 39, 147, 30, 25, 101, 145, 136, 19, 4, 48, 158, 118, 133, 49, 20, 102, 14, 151, 5, 2, 72, 103, 75, 60, 84, 34, 157, 169, 31, 161, 81, 70, 85, 159, 132, 41, 152, 179, 98, 144, 36, 16, 87, 40, 91, 1, 130, 108, 139, 94, 97, 8, 104, 13, 150, 137, 47, 73, 62, 12, 50, 61, 105, 100, 86, 146, 165, 22, 17, 57, 167, 59, 96, 120, 155, 77, 162, 55, 68, 140, 134, 82, 76, 125, 32, 176, 138, 173, 177, 163, 107, 170, 71, 129, 63, 93, 42, 52, 116, 149, 54, 128, 124, 114, 67, and 64.
According to the GW pattern of
18, 150, 165, 42, 81, 48, 63, 45, 93, 152, 25, 16, 174, 29, 47, 83, 8, 60, 30, 66, 11, 113, 44, 148, 4, 155, 59, 33, 134, 99, 32, 176, 109, 72, 36, 111, 106, 73, 170, 126, 64, 88, 20, 17, 172, 154, 120, 121, 139, 77, 98, 43, 105, 133, 19, 41, 78, 15, 7, 145, 94, 136, 131, 163, 65, 31, 96, 79, 119, 143, 10, 95, 9, 146, 14, 118, 162, 37, 97, 49, 22, 51, 127, 6, 71, 132, 87, 21, 39, 38, 54, 115, 159, 161, 84, 108, 13, 102, 135, 103, 156, 67, 173, 76, 75, 164, 52, 142, 69, 130, 56, 153, 74, 166, 158, 124, 141, 58, 116, 85, 175, 169, 168, 147, 35, 62, 5, 123, 100, 90, 122, 101, 149, 112, 140, 86, 68, 89, 125, 27, 177, 160, 0, 80, 55, 151, 53, 2, 70, 167, 114, 129, 179, 138, 1, 92, 26, 50, 28, 110, 61, 82, 91, 117, 107, 178, 34, 157, 137, 128, 40, 24, 57, 3, 171, 46, 104, 12, 144, and 23.
According to the GW pattern of
18, 8, 166, 117, 4, 111, 142, 148, 176, 91, 120, 144, 99, 124, 20, 25, 31, 78, 36, 72, 2, 98, 93, 74, 174, 52, 152, 62, 88, 75, 23, 97, 147, 15, 71, 1, 127, 138, 81, 83, 68, 94, 112, 119, 121, 89, 163, 85, 86, 28, 17, 64, 14, 44, 158, 159, 150, 32, 128, 70, 90, 29, 30, 63, 100, 65, 129, 140, 177, 46, 84, 92, 10, 33, 58, 7, 96, 151, 171, 40, 76, 6, 3, 37, 104, 57, 135, 103, 141, 107, 116, 160, 41, 153, 175, 55, 130, 118, 131, 42, 27, 133, 95, 179, 34, 21, 87, 106, 105, 108, 79, 134, 113, 26, 164, 114, 73, 102, 77, 22, 110, 161, 43, 122, 123, 82, 5, 48, 139, 60, 49, 154, 115, 146, 67, 69, 137, 109, 143, 24, 101, 45, 16, 12, 19, 178, 80, 51, 47, 149, 50, 172, 170, 169, 61, 9, 39, 136, 59, 38, 54, 156, 126, 125, 145, 0, 13, 155, 132, 162, 11, 157, 66, 165, 173, 56, 168, 167, 53, and 35.
According to the GW pattern of
77, 50, 109, 128, 153, 12, 48, 17, 147, 55, 173, 172, 135, 121, 99, 162, 52, 40, 129, 168, 103, 87, 134, 105, 179, 10, 131, 151, 3, 26, 100, 15, 123, 88, 18, 91, 54, 160, 49, 1, 76, 80, 74, 31, 47, 58, 161, 9, 16, 34, 41, 21, 177, 11, 63, 6, 39, 165, 169, 125, 114, 57, 37, 67, 93, 96, 73, 106, 83, 166, 24, 51, 142, 65, 43, 64, 53, 72, 156, 81, 4, 155, 33, 163, 56, 150, 70, 167, 107, 112, 144, 149, 36, 32, 35, 59, 101, 29, 127, 138, 176, 90, 141, 92, 170, 102, 119, 25, 75, 14, 0, 68, 20, 97, 110, 28, 89, 118, 154, 126, 2, 22, 124, 85, 175, 78, 46, 152, 23, 86, 27, 79, 130, 66, 45, 113, 111, 62, 61, 7, 30, 133, 108, 171, 143, 60, 178, 5, 122, 44, 38, 148, 157, 84, 42, 139, 145, 8, 104, 115, 71, 137, 132, 146, 164, 98, 13, 117, 174, 158, 95, 116, 140, 94, 136, 120, 82, 69, 159, and 19.
According to the GW pattern of
51, 47, 53, 43, 55, 59, 49, 33, 35, 31, 24, 37, 0, 2, 45, 41, 39, 57, 42, 44, 52, 40, 23, 30, 32, 34, 54, 56, 46, 50, 122, 48, 1, 36, 38, 58, 77, 3, 65, 81, 67, 147, 83, 69, 26, 75, 85, 73, 79, 145, 71, 63, 5, 61, 70, 78, 68, 62, 66, 6, 64, 149, 60, 82, 80, 4, 76, 84, 72, 154, 86, 74, 89, 128, 137, 91, 141, 93, 101, 7, 87, 9, 103, 99, 95, 11, 13, 143, 97, 133, 136, 12, 100, 94, 14, 88, 142, 96, 92, 8, 152, 10, 139, 102, 104, 132, 90, 98, 114, 112, 146, 123, 110, 15, 125, 150, 120, 153, 29, 106, 134, 27, 127, 108, 130, 116, 28, 107, 126, 25, 131, 124, 129, 151, 121, 105, 111, 115, 135, 148, 109, 117, 158, 113, 170, 119, 162, 178, 155, 176, 18, 20, 164, 157, 160, 22, 140, 16, 168, 166, 172, 174, 175, 179, 118, 138, 156, 19, 169, 167, 163, 173, 161, 177, 165, 144, 171, 17, 21, and 159.
According to the GW pattern of
49, 2, 57, 47, 31, 35, 24, 39, 59, 0, 45, 41, 55, 53, 51, 37, 33, 43, 56, 38, 48, 32, 50, 23, 34, 54, 1, 36, 44, 52, 40, 58, 122, 46, 42, 30, 3, 75, 73, 65, 145, 71, 79, 67, 69, 83, 85, 147, 63, 81, 77, 61, 5, 26, 62, 64, 74, 70, 82, 149, 76, 4, 78, 84, 80, 86, 66, 68, 72, 6, 60, 154, 103, 95, 101, 143, 9, 89, 141, 128, 97, 137, 133, 7, 13, 99, 91, 93, 87, 11, 136, 90, 88, 94, 10, 8, 14, 96, 104, 92, 132, 142, 100, 98, 12, 102, 152, 139, 150, 106, 146, 130, 27, 108, 153, 112, 114, 29, 110, 134, 116, 15, 127, 125, 123, 120, 148, 151, 113, 126, 124, 135, 129, 109, 25, 28, 158, 117, 105, 115, 111, 131, 107, 121, 18, 170, 164, 20, 140, 160, 166, 162, 119, 155, 168, 178, 22, 174, 172, 176, 16, 157, 159, 171, 161, 118, 17, 163, 21, 165, 19, 179, 177, 167, 138, 173, 156, 144, 169, and 175.
According to the GW pattern of
71, 38, 98, 159, 1, 32, 28, 177, 125, 102, 83, 17, 121, 151, 66, 92, 140, 6, 165, 23, 75, 91, 87, 108, 163, 50, 77, 39, 110, 128, 73, 148, 14, 5, 68, 37, 53, 93, 149, 26, 166, 48, 79, 10, 122, 150, 103, 178, 119, 101, 61, 34, 8, 86, 36, 138, 146, 72, 179, 143, 147, 89, 4, 107, 33, 144, 141, 40, 100, 29, 118, 63, 46, 20, 153, 90, 152, 124, 7, 30, 31, 43, 78, 120, 85, 25, 52, 47, 64, 81, 175, 94, 115, 15, 112, 99, 13, 21, 42, 169, 76, 19, 168, 16, 27, 162, 167, 164, 97, 82, 44, 106, 12, 109, 132, 145, 161, 174, 95, 0, 105, 134, 173, 84, 9, 65, 88, 54, 67, 116, 154, 80, 22, 172, 60, 111, 133, 56, 170, 104, 131, 123, 24, 49, 113, 136, 55, 3, 157, 156, 35, 58, 45, 155, 70, 59, 57, 171, 176, 74, 117, 18, 127, 114, 11, 69, 158, 129, 139, 62, 135, 96, 142, 41, 130, 160, 2, 126, 51, and 137.
According to the GW pattern of
66, 61, 150, 157, 63, 42, 78, 44, 23, 154, 133, 101, 82, 26, 84, 123, 89, 31, 45, 102, 36, 134, 83, 117, 170, 27, 73, 137, 25, 32, 62, 91, 4, 20, 144, 145, 21, 74, 113, 148, 24, 135, 5, 19, 2, 34, 43, 168, 14, 64, 142, 115, 87, 38, 147, 39, 51, 152, 56, 86, 122, 76, 57, 129, 172, 6, 126, 10, 97, 85, 164, 3, 80, 90, 79, 124, 138, 120, 17, 103, 99, 116, 46, 98, 162, 151, 143, 11, 175, 160, 96, 132, 81, 171, 94, 65, 118, 161, 125, 178, 95, 112, 88, 174, 13, 35, 1, 167, 0, 128, 12, 58, 29, 169, 67, 28, 119, 166, 60, 55, 54, 130, 92, 146, 177, 149, 111, 9, 173, 179, 176, 75, 77, 114, 48, 159, 8, 141, 107, 139, 52, 100, 136, 105, 127, 47, 18, 69, 109, 16, 121, 59, 163, 165, 108, 106, 70, 22, 93, 41, 33, 110, 53, 140, 153, 158, 50, 15, 37, 72, 156, 7, 131, 49, 71, 68, 104, 30, 40, 155.
According to the GW pattern of
75, 83, 11, 24, 86, 104, 156, 76, 37, 173, 127, 61, 43, 139, 106, 69, 49, 2, 128, 140, 68, 14, 100, 8, 36, 73, 148, 65, 16, 47, 177, 6, 132, 45, 5, 30, 13, 22, 29, 27, 101, 150, 23, 90, 41, 93, 89, 92, 135, 4, 71, 87, 44, 124, 26, 64, 1, 129, 157, 130, 107, 18, 91, 118, 3, 82, 144, 113, 121, 54, 84, 97, 122, 120, 7, 154, 56, 134, 57, 161, 33, 116, 28, 96, 72, 172, 12, 115, 38, 164, 32, 167, 145, 17, 88, 39, 151, 80, 0, 136, 169, 142, 74, 147, 126, 166, 163, 40, 110, 171, 50, 160, 131, 70, 175, 103, 125, 77, 162, 31, 85, 66, 67, 52, 108, 159, 133, 42, 153, 21, 51, 119, 123, 98, 35, 48, 111, 149, 25, 58, 60, 158, 102, 59, 117, 20, 141, 143, 46, 53, 155, 15, 165, 152, 112, 176, 105, 178, 99, 174, 168, 114, 179, 78, 10, 19, 62, 63, 170, 138, 34, 109, 9, 146, 95, 94, 55, 137, 81, and 79.
According to the GW pattern of
98, 159, 59, 125, 163, 89, 26, 4, 102, 70, 92, 36, 37, 142, 176, 95, 71, 19, 87, 45, 81, 47, 65, 170, 103, 48, 67, 61, 64, 35, 76, 80, 140, 77, 10, 167, 178, 155, 120, 156, 151, 12, 58, 5, 83, 137, 41, 109, 2, 66, 133, 62, 135, 28, 93, 128, 86, 57, 153, 161, 110, 52, 147, 141, 31, 79, 32, 88, 160, 84, 150, 6, 100, 73, 126, 164, 17, 42, 101, 7, 55, 105, 91, 22, 130, 154, 1, 82, 14, 0, 9, 21, 50, 165, 72, 138, 175, 106, 108, 3, 169, 30, 157, 54, 18, 20, 44, 34, 134, 107, 56, 53, 15, 162, 38, 166, 24, 33, 60, 85, 145, 115, 43, 39, 40, 124, 149, 144, 132, 96, 11, 146, 90, 129, 119, 111, 171, 8, 152, 121, 173, 131, 49, 27, 118, 16, 148, 68, 177, 94, 179, 13, 114, 75, 51, 117, 25, 46, 136, 143, 139, 113, 127, 174, 74, 29, 122, 158, 69, 97, 78, 63, 99, 112, 104, 116, 172, 168, 23, and 123.
The 1st to 33rd examples of the GW pattern for the LDPC code in which the code length N is 64 kbits can be applied to any combination of the LDPC code in which the code length N is 64 kbits with an arbitrary encoding rate r and modulation scheme (constellation).
However, when the GW pattern to be applied to the groupwise interleave is set for each combination of the code length N of the LDPC code, the encoding rate r of the LDPC code, and the modulation scheme (constellation), the error rate of each combination can be further improved.
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
<Example of GW Pattern for LDPC Code of 16 k Bits>
According to the GW pattern of
21, 41, 15, 29, 0, 23, 16, 12, 38, 43, 2, 3, 4, 20, 31, 27, 5, 33, 28, 30, 36, 8, 40, 13, 6, 9, 18, 24, 7, 39, 10, 17, 37, 1, 19, 22, 25, 26, 14, 32, 34, 11, 35, 42, and 44.
According to the GW pattern of
1, 3, 2, 8, 5, 23, 13, 12, 18, 19, 17, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 0, 4, 6, 7, 21, 16, 10, 15, 9, 11, 22, 14, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, and 44.
According to the GW pattern of
1, 4, 5, 6, 24, 21, 18, 7, 17, 12, 8, 20, 23, 29, 28, 30, 32, 34, 36, 38, 40, 42, 0, 2, 3, 14, 22, 13, 10, 25, 9, 27, 19, 16, 15, 26, 11, 31, 33, 35, 37, 39, 41, 43, and 44.
According to the GW pattern of
3, 0, 4, 7, 18, 9, 19, 27, 32, 10, 12, 24, 8, 35, 30, 17, 22, 20, 36, 38, 40, 42, 2, 5, 1, 6, 14, 15, 23, 16, 11, 21, 26, 13, 29, 33, 31, 28, 25, 34, 37, 39, 41, 43, and 44.
According to the GW pattern of
37, 0, 41, 19, 43, 8, 38, 3, 29, 13, 22, 6, 4, 2, 9, 26, 39, 15, 12, 10, 33, 17, 20, 16, 21, 44, 42, 27, 7, 11, 30, 34, 24, 1, 23, 35, 36, 25, 31, 18, 28, 32, 40, 5, and 14.
According to the GW pattern of
6, 28, 17, 4, 3, 38, 13, 41, 44, 43, 7, 40, 19, 2, 23, 16, 37, 15, 30, 20, 11, 8, 1, 27, 32, 34, 33, 39, 5, 9, 10, 18, 0, 31, 29, 26, 14, 21, 42, 22, 12, 24, 35, 25, and 36.
According to the GW pattern of
27, 11, 20, 1, 7, 5, 29, 35, 9, 10, 34, 18, 25, 28, 6, 13, 17, 0, 23, 16, 41, 15, 19, 44, 24, 37, 4, 31, 8, 32, 14, 42, 12, 2, 40, 30, 36, 39, 43, 21, 3, 22, 26, 33, and 38.
According to the GW pattern of
3, 6, 7, 27, 2, 23, 10, 30, 22, 28, 24, 20, 37, 21, 4, 14, 11, 42, 16, 9, 15, 26, 33, 40, 5, 8, 44, 34, 18, 0, 32, 29, 19, 41, 38, 17, 25, 43, 35, 36, 13, 39, 12, 1, and 31.
According to the GW pattern of
31, 38, 7, 9, 13, 21, 39, 12, 10, 1, 43, 15, 30, 0, 14, 3, 42, 34, 40, 24, 28, 35, 8, 11, 23, 4, 20, 17, 41, 19, 5, 37, 22, 32, 18, 2, 26, 44, 25, 33, 36, 27, 16, 6, and 29.
According to the GW pattern of
36, 6, 2, 20, 43, 17, 33, 22, 23, 25, 13, 0, 10, 7, 21, 1, 19, 26, 8, 14, 31, 35, 16, 5, 29, 40, 11, 9, 4, 34, 15, 42, 32, 28, 18, 37, 30, 39, 24, 41, 3, 38, 27, 12, and 44.
According to the GW pattern of
14, 22, 18, 11, 28, 26, 2, 38, 10, 0, 5, 12, 24, 17, 29, 16, 39, 13, 23, 8, 25, 43, 34, 33, 27, 15, 7, 1, 9, 35, 40, 32, 30, 20, 36, 31, 21, 41, 44, 3, 42, 6, 19, 37, and 4.
According to the GW pattern of
17, 11, 14, 7, 31, 10, 2, 26, 0, 32, 29, 22, 33, 12, 20, 28, 27, 39, 37, 15, 4, 5, 8, 13, 38, 18, 23, 34, 24, 6, 1, 9, 16, 44, 21, 3, 36, 30, 40, 35, 43, 42, 25, 19, and 41.
According to the GW pattern of
1, 27, 17, 30, 11, 15, 9, 7, 5, 6, 32, 33, 2, 14, 3, 39, 18, 12, 29, 13, 41, 31, 4, 43, 35, 34, 40, 10, 19, 44, 8, 26, 21, 16, 28, 0, 23, 38, 25, 36, 22, 37, 42, 24, and 20.
According to the GW pattern of
41, 2, 12, 6, 33, 1, 13, 11, 26, 10, 39, 43, 36, 23, 42, 7, 44, 20, 8, 38, 18, 22, 24, 40, 4, 28, 29, 19, 14, 5, 9, 0, 30, 25, 35, 37, 27, 32, 31, 34, 21, 3, 15, 17, and 16,
According to the GW pattern of
17, 2, 30, 12, 7, 25, 27, 3, 15, 14, 4, 26, 34, 31, 13, 22, 0, 39, 23, 24, 21, 6, 38, 5, 19, 42, 11, 32, 28, 40, 20, 18, 36, 9, 41, 10, 33, 37, 1, 16, 8, 43, 29, 35, and 44.
According to the GW pattern of
28, 21, 10, 15, 8, 22, 26, 2, 14, 1, 27, 3, 39, 20, 34, 25, 12, 6, 7, 40, 30, 29, 38, 16, 43, 33, 4, 35, 9, 32, 5, 36, 0, 41, 37, 18, 17, 13, 24, 42, 31, 23, 19, 11, and 44.
The 1st to 16th examples of the GW pattern for the LDPC code in which the code length N is 16 kbits can be applied to any combination of the LDPC code in which the code length N is 16 kbits with an arbitrary encoding rate r and modulation scheme (constellation).
However, when the GW pattern to be applied to the groupwise interleave is set for each combination of the code length N of the LDPC code, the encoding rate r of the LDPC code, and the modulation scheme (constellation), the error rate of each combination can be further improved.
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
When the GW pattern of
<Simulation Result>
In
As can be seen from
Further, it is possible to apply the GW patterns of
Further, it is possible to apply the GW pattern of
<Configuration Example of Receiving Device 12>
An OFDM operating unit 151 receives an OFDM signal from the transmitting device 11 (
The frame managing unit 152 executes processing (frame interpretation) of a frame configured by the data supplied from the OFDM operating unit 151 and supplies a signal of target data obtained as a result and a signal of signaling to frequency deinterleavers 161 and 153.
The frequency deinterleaver 153 performs frequency deinterleave in a unit of symbol, with respect to the data supplied from the frame managing unit 152, and supplies the symbol to a demapper 154.
The demapper 154 performs demapping (signal point arrangement decoding) and orthogonal demodulation on the data (the data on the constellation) supplied from the frequency deinterleaver 153 based on the arrangement (constellation) of the signal points decided according to the orthogonal modulation performed at the transmitting device 11 side, and supplies the data ((the likelihood of) the LDPC code) obtained as a result to the LDPC decoder 155.
The LDPC decoder 155 performs LDPC decoding of the LDPC code supplied from the demapper 154 and supplies LDPC target data (in this case, a BCH code) obtained as a result to a BCH decoder 156.
The BCH decoder 156 performs BCH decoding of the LDPC target data supplied from the LDPC decoder 155 and outputs control data (signaling) obtained as a result.
Meanwhile, the frequency deinterleaver 161 performs frequency deinterleave in a unit of symbol, with respect to the data supplied from the frame managing unit 152, and supplies the symbol to a SISO/MISO decoder 162.
The SISO/MISO decoder 162 performs spatiotemporal decoding of the data supplied from the frequency deinterleaver 161 and supplies the data to a time deinterleaver 163.
The time deinterleaver 163 performs time deinterleave in a unit of symbol, with respect to the data supplied from the SISO/MISO decoder 162, and supplies the data to a demapper 164.
The demapper 164 performs demapping (signal point arrangement decoding) and orthogonal demodulation on the data (the data on the constellation) supplied from the time deinterleaver 163 based on the arrangement (constellation) of the signal points decided according to the orthogonal modulation performed at the transmitting device 11 side, and supplies the data obtained as a result to a bit deinterleaver 165.
The bit deinterleaver 165 perform the bit deinterleave on the data supplied from the demapper 164, and supplies (the likelihood of) the LDPC code serving as the data that has undergone the bit deinterleave to an LDPC decoder 166.
The LDPC decoder 166 performs LDPC decoding of the LDPC code supplied from the bit deinterleaver 165 and supplies LDPC target data (in this case, a BCH code) obtained as a result to a BCH decoder 167.
The BCH decoder 167 performs BCH decoding of the LDPC target data supplied from the LDPC decoder 155 and supplies data obtained as a result to a BB descrambler 168.
The BB descrambler 168 executes BB descramble with respect to the data supplied from the BCH decoder 167 and supplies data obtained as a result to a null deletion unit 169.
The null deletion unit 169 deletes null inserted by the padder 112 of
The demultiplexer 170 individually separates one or more streams (target data) multiplexed with the data supplied from the null deletion unit 169, performs necessary processing to output the streams as output streams.
Here, the receiving device 12 can be configured without including part of the blocks illustrated in
<Configuration Example of Bit Deinterleaver 165>
The bit deinterleaver 165 is configured with a block deinterleaver 54 and a groupwise deinterleaver 55, and performs the (bit) deinterleave of the symbol bits of the symbol serving as the data supplied from the demapper 164 (
In other words, the block deinterleaver 54 performs the block deinterleave (the inverse process of the block interleave) corresponding to the block interleave performed by the block interleaver 25 of
The groupwise deinterleaver 55 performs the groupwise deinterleave (the inverse process of the groupwise interleave) corresponding to the groupwise interleave performed by the groupwise interleaver 24 of
Here, when the LDPC code supplied from the demapper 164 to the bit deinterleaver 165 has undergone the parity interleave, the groupwise interleave, and the block interleave, the bit deinterleaver 165 can perform all of the parity deinterleave (the inverse process of the parity interleave, that is, the parity deinterleave of restoring the code bits of the LDPC code whose sequence has been changed by the parity interleave to the original sequence) corresponding to the parity interleave, the block deinterleave corresponding to the block interleave, and the groupwise deinterleave corresponding to the groupwise interleave.
However, the bit deinterleaver 165 of
Thus, the LDPC code that has undergone the block deinterleave and groupwise deinterleave but has not undergone the parity deinterleave is supplied from (the groupwise deinterleaver 55 of) the bit deinterleaver 165 to the LDPC decoder 166.
The LDPC decoder 166 performs LDPC decoding of the LDPC code supplied from the bit deinterleaver 165 using the transformed parity check matrix obtained by performing at least the column permutation corresponding to the parity interleave on the parity check matrix H of the DVB scheme used for the LDPC encoding by the LDPC encoder 115 of
In step S111, the demapper 164 performs demapping and orthogonal demodulation on the data (the data on the constellation mapped to the signal points) supplied from the time deinterleaver 163, and supplies the resulting data to the bit deinterleaver 165, and the process proceeds to step S112.
In step S112, the bit deinterleaver 165 performs the deinterleave (the bit deinterleave) on the data supplied from the demapper 164, and the process proceeds to step S113.
In other words, in step S112, in the bit deinterleaver 165, the block deinterleaver 54 performs the block deinterleave on the data (symbol) supplied from the demapper 164, and supplies the code bits of the LDPC code obtained as a result to the groupwise deinterleaver 55.
The groupwise deinterleaver 55 performs the groupwise deinterleave on the LDPC code supplied from the block deinterleaver 54, and supplies (the likelihood of) the LDPC code obtained as a result to the LDPC decoder 166.
In step S113, the LDPC decoder 166 performs LDPC decoding of the LDPC code supplied from the groupwise deinterleaver 55 using the parity check matrix H used for the LDPC encoding by the LDPC encoder 115 of
In
<LDPC Decoding>
The LDPC decoding performed by the LDPC decoder 166 of
As described above, the LDPC decoder 166 of
In this case, LDPC decoding that can suppress an operation frequency at a sufficiently realizable range while suppressing a circuit scale, by performing the LDPC decoding using the transformed parity check matrix, is previously suggested (for example, refer to JP 4224777B).
Therefore, first, the previously suggested LDPC decoding using the transformed parity check matrix will be described with reference to
In
In the parity check matrix H of
Row Replacement: (6s+t+1)th row→(5t+s+1)th row (11)
Column Replacement: (6x+y+61)th column→(5y+x+61)th column (12)
In the expressions (11) and (12), s, t, x, and y are integers in ranges of 0≤s<5, 0≤t<6, 0≤x<5, and 0≤t<6, respectively.
According to the row replacement of the expression (11), replacement is performed such that the 1st, 7th, 13rd, 19th, and 25th rows having remainders of 1 when being divided by 6 are replaced with the 1st, 2nd, 3rd, 4th, and 5th rows, and the 2nd, 8th, 14th, 20th, and 26th rows having remainders of 2 when being divided by 6 are replaced with the 6th, 7th, 8th, 9th, and 10th rows, respectively.
According to the column replacement of the expression (12), replacement is performed such that the 61st, 67th, 73rd, 79th, and 85th columns having remainders of 1 when being divided by 6 are replaced with the 61st, 62nd, 63rd, 64th, and 65th columns, respectively, and the 62nd, 68th, 74th, 80th, and 86th columns having remainders of 2 when being divided by 6 are replaced with the 66th, 67th, 68th, 69th, and 70th columns, respectively, with respect to the 61st and following columns (parity matrix).
In this way, a matrix that is obtained by performing the replacements of the rows and the columns with respect to the parity check matrix H of
In this case, even when the row replacement of the parity check matrix H is performed, the sequence of the code bits of the LDPC code is not influenced.
The column replacement of the expression (12) corresponds to parity interleave to interleave the (K+qx+y+1)th code bit into the position of the (K+Py+x+1)th code bit, when the information length K is 60, the unit size P is 5, and the divisor q (=M/P) of the parity length M (in this case, 30) is 6.
Therefore, the parity check matrix H′ in
If the parity check matrix H′ of
Thereby, the transformed parity check matrix H′ of
Therefore, the column replacement of the expression (12) is performed with respect to the LDPC code of the original parity check matrix H, the LDPC code c′ after the column replacement is decoded (LDPC decoding) using the transformed parity check matrix H′ of
In
The transformed parity check matrix H′ of
When the LDPC code represented by the parity check matrix represented by the P×P constitutive matrixes is decoded, an architecture in which P check node operations and variable node operations are simultaneously performed can be used.
That is,
The decoding device of
First, a method of storing data in the branch data storing memories 300 and 304 will be described.
The branch data storing memory 300 includes the 6 FIFOs 300_{1 }to 300_{6 }that correspond to a number obtained by dividing a row number 30 of the transformed parity check matrix H′ of
In the FIFO 300_{1}, data (messages v_{i }from variable nodes) corresponding to positions of 1 in the first to fifth rows of the transformed parity check matrix H′ of
In the FIFO 300_{2}, data corresponding to positions of 1 in the sixth to tenth rows of the transformed parity check matrix H′ of
That is, with respect to a constitutive matrix of which the weight is two or more, when the constitutive matrix is represented by a sum of multiple parts of a P×P unit matrix of which the weight is 1, a quasi unit matrix in which one or more elements of 1 in the unit matrix become 0, or a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, data (messages corresponding to branches belonging to the unit matrix, the quasi unit matrix, or the shifted matrix) corresponding to the positions of 1 in the unit matrix of the weight of 1, the quasi unit matrix, or the shifted matrix is stored at the same address (the same FIFO among the FIFOs 300_{1 }to 300_{6}).
Subsequently, in the storage regions of the third to ninth steps, data is stored in association with the transformed parity check matrix H′, similar to the above case.
In the FIFOs 300_{3 }to 300_{6}, data is stored in association with the transformed parity check matrix H′, similar to the above case.
The branch data storing memory 304 includes 18 FIFOs 304_{1 }to 304_{18 }that correspond to a number obtained by dividing a column number 90 of the transformed parity check matrix H′ by 5 to be a column number of a constitutive matrix (the unit size P). The FIFO 304_{x }(x=1, 2, . . . , and 18) includes a plurality of steps of storage regions. In the storage region of each step, messages corresponding to five branches corresponding to a row number and a column number of the constitutive matrix (the unit size P) can be simultaneously read or written.
In the FIFO 304_{1}, data (messages u_{j }from check nodes) corresponding to positions of 1 in the first to fifth columns of the transformed parity check matrix H′ of
That is, with respect to a constitutive matrix of which the weight is two or more, when the constitutive matrix is represented by a sum of multiple parts of a P×P unit matrix of which the weight is 1, a quasi unit matrix in which one or more elements of 1 in the unit matrix become 0, or a shifted matrix obtained by cyclically shifting the unit matrix or the quasi unit matrix, data (messages corresponding to branches belonging to the unit matrix, the quasi unit matrix, or the shifted matrix) corresponding to the positions of 1 in the unit matrix of the weight of 1, the quasi unit matrix, or the shifted matrix is stored at the same address (the same FIFO among the FIFOs 304_{1 }to 304_{18}).
Subsequently, in the storage regions of the fourth and fifth steps, data is stored in association with the transformed parity check matrix H′, similar to the above case. The number of steps of the storage regions of the FIFO 304_{1 }becomes 5 to be a maximum number of the number (Hamming weight) of 1 of a row direction in the first to fifth columns of the transformed parity check matrix H′.
In the FIFOs 304_{2 }and 304_{3}, data is stored in association with the transformed parity check matrix H′, similar to the above case, and each length (the number of steps) is 5. In the FIFOs 304_{4 }to 304_{12}, data is stored in association with the transformed parity check matrix H′, similar to the above case, and each length is 3. In the FIFOs 304_{13 }to 304_{18}, data is stored in association with the transformed parity check matrix H′, similar to the above case, and each length is 2.
Next, an operation of the decoding device of
The branch data storing memory 300 includes the 6 FIFOs 300_{1 }to 300_{6}. According to information (matrix data) D312 on which row of the transformed parity check matrix H′ in
The selector 301 selects the five messages from the FIFO from which data is currently read, among the FIFOs 300_{1 }to 300_{6}, according to a select signal D301, and supplies the selected messages as messages D302 to the check node calculating unit 302.
The check node calculating unit 302 includes five check node calculators 302_{1 }to 302_{5}. The check node calculating unit 302 performs a check node operation according to the expression (7), using the messages D302 (D302_{1 }to D302_{5}) (messages v_{i }of the expression 7) supplied through the selector 301, and supplies five messages D303 (D303_{1 }to D303_{5}) (messages u_{j }of the expression (7)) obtained as a result of the check node operation to a cyclic shift circuit 303.
The cyclic shift circuit 303 cyclically shifts the five messages D303_{1 }to D303_{5 }calculated by the check node calculating unit 302, on the basis of information (matrix data) D305 on how many the unit matrixes (or the quasi unit matrix) becoming the origin in the transformed parity check matrix H′ are cyclically shifted to obtain the corresponding branches, and supplies a result as messages D304 to the branch data storing memory 304.
The branch data storing memory 304 includes the eighteen FIFOs 304_{1 }to 304_{18}. According to information D305 on which row of the transformed parity check matrix H′ five messages D304 supplied from a cyclic shift circuit 303 of a previous step belongs to, the FIFO storing data is selected from the FIFOs 304_{1 }to 304_{18 }and the five messages D304 are collectively stored sequentially in the selected FIFO. When the data is read, the branch data storing memory 304 sequentially reads the five messages D304_{1 }from the FIFO 304_{1 }and supplies the messages to the selector 305 of a next step. After reading of the messages from the FIFO 304_{1 }ends, the branch data storing memory 304 reads the messages sequentially from the FIFOs 304_{2 }to 304_{18 }and supplies the messages to the selector 305.
The selector 305 selects the five messages from the FIFO from which data is currently read, among the FIFOs 304_{1 }to 304_{18}, according to a select signal D307, and supplies the selected messages as messages D308 to the variable node calculating unit 307 and the decoding word calculating unit 309.
Meanwhile, the reception data rearranging unit 310 rearranges the LDPC code D313, that is corresponding to the parity check matrix H in
The variable node calculating unit 307 includes five variable node calculators 307_{1 }to 307_{5}. The variable node calculating unit 307 performs the variable node operation according to the expression (1), using the messages D308 (D308_{1 }to D308_{5}) (messages u_{j }of the expression (1)) supplied through the selector 305 and the five reception values D309 (reception values u_{0i }of the expression (1)) supplied from the reception data memory 306, and supplies messages D310 (D310_{1 }to D310_{5}) (message v_{i }of the expression (1)) obtained as an operation result to the cyclic shift circuit 308.
The cyclic shift circuit 308 cyclically shifts the messages D310_{1 }to D310_{5 }calculated by the variable node calculating unit 307, on the basis of information on how many the unit matrixes (or the quasi unit matrix) becoming the origin in the transformed parity check matrix H′ are cyclically shifted to obtain the corresponding branches, and supplies a result as messages D311 to the branch data storing memory 300.
By circulating the above operation in one cycle, decoding (variable node operation and check node operation) of the LDPC code can be performed once. After decoding the LDPC code by the predetermined number of times, the decoding device of
That is, the decoding word calculating unit 309 includes five decoding word calculators 309_{1 }to 309_{5}. The decoding word calculating unit 309 calculates a decoding result (decoding word) on the basis of the expression (5), as a final step of multiple decoding, using the five messages D308 (D308_{1 }to D308_{5}) (messages u_{j }of the expression) output by the selector 305 and the five reception values D309 (reception values u_{0i }of the expression (5)) supplied from the reception data memory 306, and supplies decoded data D315 obtained as a result to the decoded data rearranging unit 311.
The decoded data rearranging unit 311 performs the reverse replacement of the column replacement of the expression (12) with respect to the decoded data D315 supplied from the decoding word calculating unit 309, rearranges the order thereof, and outputs the decoded data as a final decoding result D316.
As mentioned above, by performing one or both of row replacement and column replacement on the parity check matrix (original parity check matrix) and converting it into a parity check matrix (transformed parity check matrix) that can be shown by the combination of a p×p unit matrix, a quasi unit matrix in which one or more elements of 1 thereof become 0, a shifted matrix that cyclically shifts the unit matrix or the quasi unit matrix, a sum matrix that is the sum of two or more of the unit matrix, the quasi unit matrix and the shifted matrix, and a p×p 0 matrix, that is, the combination of constitutive matrixes, as for LDPC code decoding, it becomes possible to adopt architecture that simultaneously performs check node calculation and variable node calculation by P which is the number less than the row number and column number of the parity check matrix. In the case of adopting the architecture that simultaneously performs node calculation (check node calculation and variable node calculation) by P which is the number less than the row number and column number of the parity check matrix, as compared with a case where the node calculation is simultaneously performed by the number equal to the row number and column number of the parity check matrix, it is possible to suppress the operation frequency within a feasible range and perform many items of iterative decoding.
The LDPC decoder 166 that constitutes the receiving device 12 of
That is, for the simplification of explanation, if the parity check matrix of the LDPC code output by the LDPC encoder 115 constituting the transmitting device 11 of
Because the parity interleave corresponds to the column replacement of the expression (12) as described above, it is not necessary to perform the column replacement of the expression (12) in the LDPC decoder 166.
For this reason, in the receiving device 12 of
That is,
In
As described above, because the LDPC decoder 166 can be configured without providing the reception data rearranging unit 310, a scale can be decreased as compared with the decoding device of
In
That is, in the transmitting device 11 of
Further, when the parity portion of the decoding result is unnecessary, and only the information bits of the decoding result are output after the decoding of the LDPC code by the LDPC decoder 166, the LDPC decoder 166 may be configured without the decoded data rearranging unit 311.
<Configuration Example of Block Deinterleaver 54>
The block deinterleaver 54 has a similar configuration to the block interleaver 25 described above with reference to
Thus, the block deinterleaver 54 includes the storage region called the part 1 and the storage region called the part 2, and each of the parts 1 and 2 is configured such that a number C of columns equal in number to the number m of bits of the symbol and serving as storage regions that store one bit in the row (horizontal) direction and store a predetermined number of bits in the column (vertical) direction are arranged.
The block deinterleaver 54 performs the block deinterleave by writing the LDPC code in the parts 1 and 2 and reading the LDPC code from the parts 1 and 2.
However, in the block deinterleave, the writing of the LDPC code (serving as the symbol) is performed in the order in which the LDPC code is read by the block interleaver 25 of
Further, in the block deinterleave, the reading of the LDPC code is performed in the order in which the LDPC code is written by the block interleaver 25 of
In other words, in the block interleave performed by the block interleaver 25 of
<Other Configuration Example of Bit Deinterleaver 165>
In the drawings, portions that correspond to the case of
That is, the bit deinterleaver 165 of
Referring to
In other words, the block deinterleaver 54 performs the block deinterleave (the inverse process of the block interleave) corresponding to the block interleave performed by the block interleaver 25 of the transmitting device 11, that is, the block deinterleave of restoring the positions of the code bits rearranged by the block interleave to the original positions on the LDPC code supplied from the demapper 164, and supplies the LDPC code obtained as a result to the groupwise deinterleaver 55.
The groupwise deinterleaver 55 performs the groupwise deinterleave corresponding to the groupwise interleave serving as the rearrangement process performed by the groupwise interleaver 24 of the transmitting device 11 on the LDPC code supplied from the block deinterleaver 54.
The LDPC code that is obtained as a result of the groupwise deinterleave is supplied from the groupwise deinterleaver 55 to the parity deinterleaver 1011.
The parity deinterleaver 1011 performs the parity deinterleave (reverse processing of the parity interleave) corresponding to the parity interleave performed by the parity interleaver 23 of the transmitting device 11, that is, the parity deinterleave to restore the sequence of the code bits of the LDPC code of which a sequence is changed by the parity interleave to the original sequence, with respect to the code bits after the groupwise deinterleave in the groupwise deinterleaver 55.
The LDPC code that is obtained as a result of the parity deinterleave is supplied from the parity deinterleaver 1011 to the LDPC decoder 166.
Therefore, in the bit deinterleaver 165 of
The LDPC decoder 166 performs the LDPC decoding of the LDPC code supplied from the bit deinterleaver 165 using the parity check matrix H used for the LDPC encoding by the LDPC encoder 115 of the transmitting device 11. In other words, the LDPC decoder 166 performs the LDPC decoding of the LDPC code supplied from the bit deinterleaver 165 using the parity check matrix H (of the DVB scheme) used for the LDPC encoding by the LDPC encoder 115 of the transmitting device 11 or the transformed parity check matrix obtained by performing at least the column permutation corresponding to the parity interleave on the parity check matrix H (for the ETRI scheme, the parity check matrix (
In
In the LDPC decoder 166, when the LDPC decoding of the LDPC code is performed using the transformed parity check matrix obtained by performing at least the column replacement corresponding to the parity interleave with respect to the parity check matrix H (of the DVB method) used by the LDPC encoder 115 of the transmitting device 11 to perform the LDPC encoding (for the ETRI scheme, the transformed parity check matrix (
In
<Configuration Example of Reception System>
In
The acquiring unit 1101 acquires a signal including an LDPC code obtained by performing at least LDPC encoding with respect to LDPC target data such as image data or sound data of a program, through a transmission path (communication path) not illustrated in the drawings, such as terrestrial digital broadcasting, satellite digital broadcasting, a CATV network, the Internet, or other networks, and supplies the signal to the transmission path decoding processing unit 1102.
In this case, when the signal acquired by the acquiring unit 1101 is broadcast from a broadcasting station through a ground wave, a satellite wave, or a CATV (Cable Television) network, the acquiring unit 1101 is configured using a tuner and an STB (Set Top Box). When the signal acquired by the acquiring unit 1101 is transmitted from a web server by multicasting like an IPTV (Internet Protocol Television), the acquiring unit 1101 is configured using a network I/F (Interface) such as an NIC (Network Interface Card).
The transmission path decoding processing unit 1102 corresponds to the receiving device 12. The transmission path decoding processing unit 1102 executes transmission path decoding processing including at least processing for correcting error generated in a transmission path, with respect to the signal acquired by the acquiring unit 1101 through the transmission path, and supplies a signal obtained as a result to the information source decoding processing unit 1103.
That is, the signal that is acquired by the acquiring unit 1101 through the transmission path is a signal that is obtained by performing at least error correction encoding to correct the error generated in the transmission path. The transmission path decoding processing unit 1102 executes transmission path decoding processing such as error correction processing, with respect to the signal.
As the error correction encoding, for example, LDPC encoding or BCH encoding exists. In this case, as the error correction encoding, at least the LDPC encoding is performed.
The transmission path decoding processing includes demodulation of a modulation signal.
The information source decoding processing unit 1103 executes information source decoding processing including at least processing for extending compressed information to original information, with respect to the signal on which the transmission path decoding processing is executed.
That is, compression encoding that compresses information may be performed with respect to the signal acquired by the acquiring unit 1101 through the transmission path to decrease a data amount of an image or a sound corresponding to information. In this case, the information source decoding processing unit 1103 executes the information source decoding processing such as the processing (extension processing) for extending the compressed information to the original information, with respect to the signal on which the transmission path decoding processing is executed.
When the compression encoding is not performed with respect to the signal acquired by the acquiring unit 1101 through the transmission path, the processing for extending the compressed information to the original information is not executed in the information source decoding processing unit 1103.
In this case, as the extension processing, for example, MPEG decoding exists. In the transmission path decoding processing, in addition to the extension processing, descramble may be included.
In the reception system that is configured as described above, in the acquiring unit 1101, a signal in which the compression encoding such as the MPEG encoding and the error correction encoding such as the LDPC encoding are performed with respect to data such as an image or a sound is acquired through the transmission path and is supplied to the transmission path decoding processing unit 1102.
In the transmission path decoding processing unit 1102, the same processing as the receiving device 12 executes as the transmission path decoding processing with respect to the signal supplied from the acquiring unit 1101 and a signal obtained as a result is supplied to the information source decoding processing unit 1103.
In the information source decoding processing unit 1103, the information source decoding processing such as the MPEG decoding is executed with respect to the signal supplied from the transmission path decoding processing unit 1102 and an image or a sound obtained as a result is output.
The reception system of
Each of the acquiring unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device (hardware (IC (Integrated Circuit) and the like) or software module).
With respect to the acquiring unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103, each of a set of the acquiring unit 1101 and the transmission path decoding processing unit 1102, a set of the transmission path decoding processing unit 1102 and the information source decoding processing unit 1103, and a set of the acquiring unit 1101, the transmission path decoding processing unit 1102, and the information source decoding processing unit 1103 can be configured as one independent device.
In the drawings, portions that correspond to the case of
The reception system of
The output unit 1111 is a display device to display an image or a speaker to output a sound and outputs an image or a sound corresponding to a signal output from the information source decoding processing unit 1103. That is, the output unit 1111 displays the image or outputs the sound.
The reception system of
When the compression encoding is not performed with respect to the signal acquired in the acquiring unit 1101, the signal that is output by the transmission path decoding processing unit 1102 is supplied to the output unit 1111.
In the drawings, portions that correspond to the case of
The reception system of
However, the reception system of
The recording unit 1121 records (stores) a signal (for example, TS packets of TS of MPEG) output by the transmission path decoding processing unit 1102 on recording (storage) media such as an optical disk, a hard disk (magnetic disk), and a flash memory.
The reception system of
In
<Embodiment of Computer>
Next, the series of processing described above can be executed by hardware or can be executed by software. In the case in which the series of processing is executed by the software, a program configuring the software is installed in a generalpurpose computer.
Therefore,
The program can be previously recorded on a hard disk 705 and a ROM 703 corresponding to recording media embedded in the computer.
Alternatively, the program can be temporarily or permanently stored (recorded) on removable recording media 711 such as a flexible disk, a CDROM (Compact Disc Read Only Memory), an MO (Magneto Optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory. The removable recording media 711 can be provided as socalled package software.
The program is installed from the removable recording media 711 to the computer. In addition, the program can be transmitted from a download site to the computer by wireless through an artificial satellite for digital satellite broadcasting or can be transmitted to the computer by wire through a network such as a LAN (Local Area Network) or the Internet. The computer can receive the program transmitted as described above by a communication unit 708 and install the program in the embedded hard disk 705.
The computer includes a CPU (Central Processing Unit) 702 embedded therein. An input/output interface 710 is connected to the CPU 702 through a bus 701. If a user operates an input unit 707 configured using a keyboard, a mouse, and a microphone and a command is input through the input/output interface 710, the CPU 702 executes the program stored in the ROM (Read Only Memory) 703, according to the command. Alternatively, the CPU 702 loads the program stored in the hard disk 705, the program transmitted from a satellite or a network, received by the communication unit 708, and installed in the hard disk 705, or the program read from the removable recording media 711 mounted to a drive 709 and installed in the hard disk 705 to the RAM (Random Access Memory) 704 and executes the program. Thereby, the CPU 702 executes the processing according to the flowcharts described above or the processing executed by the configurations of the block diagrams described above. In addition, the CPU 702 outputs the processing result from the output unit 706 configured using an LCD (Liquid Crystal Display) or a speaker, transmits the processing result from the communication unit 708, and records the processing result on the hard disk 705, through the input/output interface 710, according to necessity.
In the present specification, it is not necessary to process the processing steps describing the program for causing the computer to execute the various processing in time series according to the order described as the flowcharts and processing executed in parallel or individually (for example, parallel processing or processing using an object) is also included.
The program may be processed by one computer or may be processed by a plurality of computers in a distributed manner. The program may be transmitted to a remote computer and may be executed.
An embodiment of the disclosure is not limited to the embodiments described above, and various changes and modifications may be made without departing from the scope of the disclosure.
That is, for example, (the parity check matrix initial value table of) the abovedescribed new LDPC code can be used even if the communication path 13 (
The GW patterns can be applied to a code other than the new LDPC code. Further, the modulation scheme to which the GW patterns are applied is not limited to QPSK, 16QAM, 64QAM, 256QAM, 1024QAM, and 4096QAM.
The effects described in this specification are merely examples and not limited, and any other effect may be obtained.
 11 transmitting device
 12 receiving device
 23 parity interleaver
 24 groupwise interleaver
 25 block interleaver
 54 block deinterleaver
 55 groupwise deinterleaver
 111 mode adaptation/multiplexer
 112 padder
 113 BB scrambler
 114 BCH encoder
 115 LDPC encoder
 116 bit interleaver
 117 mapper
 118 time interleaver
 119 SISO/MISO encoder
 120 frequency interleaver
 121 BCH encoder
 122 LDPC encoder
 123 mapper
 124 frequency interleaver
 131 frame builder/resource allocation unit
 132 OFDM generating unit
 151 OFDM operating unit
 152 frame managing unit
 153 frequency deinterleaver
 154 demapper
 155 LDPC decoder
 156 BCH decoder
 161 frequency deinterleaver
 162 SISO/MISO decoder
 163 time deinterleaver
 164 demapper
 165 bit deinterleaver
 166 LDPC decoder
 167 BCH decoder
 168 BB descrambler
 169 null deletion unit
 170 demultiplexer
 300 branch data storing memory
 301 selector
 302 check node calculating unit
 303 cyclic shift circuit
 304 branch data storing memory
 305 selector
 306 reception data memory
 307 variable node calculating unit
 308 cyclic shift circuit
 309 decoding word calculating unit
 310 reception data rearranging unit
 311 decoded data rearranging unit
 601 encoding processing unit
 602 storage unit
 611 encoding rate setting unit
 612 initial value table reading unit
 613 parity check matrix generating unit
 614 information bit reading unit
 615 encoding parity operation unit
 616 control unit
 701 bus
 702 CPU
 703 ROM
 704 RAM
 705 hard disk
 706 output unit
 707 input unit
 708 communication unit
 709 drive
 710 input/output interface
 711 removable recording media
 1001 reverse interchanging unit
 1002 memory
 1011 parity deinterleaver
 1101 acquiring unit
 1101 transmission path decoding processing unit
 1103 information source decoding processing unit
 1111 output unit
 1121 recording unit