RSA decryption processor and method for controlling RSA decryption processor
First Claim
1. An RSA decryption processor, comprising a memory, a control component, a preprocessing circuit unit and a parallel processor, whereinthe memory is configured to store decryption parameters comprising a private key, and a preset first factor and second factor prime with each other;
- the control component is configured to receive a ciphertext set, send a preprocessing signal comprising the ciphertext set to the preprocessing circuit unit, in response to that a ciphertext bit width of the ciphertext set is greater than a predetermined threshold, and send a decryption signal comprising the ciphertext set to the parallel processor in response to that the ciphertext bit width of the ciphertext set is not greater than the predetermined threshold;
the preprocessing circuit unit is configured to;
read a decryption parameter from the memory in response to receiving the preprocessing signal, and perform an operation on the decryption parameter and a ciphertext whose bit width is greater than the predetermined threshold in the ciphertext set according to the Chinese remainder theorem, to determine intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold, wherein the intermediate parameters comprise a first base, a first exponent, a second base, and a second exponent;
the control component is further configured to;
monitor the preprocessing circuit unit, and determine whether a modular exponentiation circuit unit in the parallel processor is idle, in response to detecting that the preprocessing circuit unit completes determining the intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold; and
the parallel processor is configured to;
read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts.
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Abstract
The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.
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Citations
13 Claims
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1. An RSA decryption processor, comprising a memory, a control component, a preprocessing circuit unit and a parallel processor, wherein
the memory is configured to store decryption parameters comprising a private key, and a preset first factor and second factor prime with each other; -
the control component is configured to receive a ciphertext set, send a preprocessing signal comprising the ciphertext set to the preprocessing circuit unit, in response to that a ciphertext bit width of the ciphertext set is greater than a predetermined threshold, and send a decryption signal comprising the ciphertext set to the parallel processor in response to that the ciphertext bit width of the ciphertext set is not greater than the predetermined threshold; the preprocessing circuit unit is configured to;
read a decryption parameter from the memory in response to receiving the preprocessing signal, and perform an operation on the decryption parameter and a ciphertext whose bit width is greater than the predetermined threshold in the ciphertext set according to the Chinese remainder theorem, to determine intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold, wherein the intermediate parameters comprise a first base, a first exponent, a second base, and a second exponent;the control component is further configured to;
monitor the preprocessing circuit unit, and determine whether a modular exponentiation circuit unit in the parallel processor is idle, in response to detecting that the preprocessing circuit unit completes determining the intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold; andthe parallel processor is configured to;
read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory, a preprocessing circuit unit and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and a preset first factor and second factor prime with each other, and the method comprises:
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receiving a ciphertext set; sending a preprocessing signal comprising the ciphertext set to the preprocessing circuit unit, in response to that a ciphertext bit width of the ciphertext set is greater than a predetermined threshold, so that the preprocessing circuit unit reads a decryption parameter from the memory in response to receiving the preprocessing signal, and performs an operation on the decryption parameter and a ciphertext whose bit width is greater than the predetermined threshold in the ciphertext set according to the Chinese remainder theorem, to determine intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold, wherein the intermediate parameters comprise a first base, a first exponent, a second base, and a second exponent;
sending a decryption signal comprising the ciphertext set to the parallel processor in response to that the ciphertext bit width of the ciphertext set is not greater than the predetermined threshold, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts;monitoring the preprocessing circuit unit; and determining whether a modular exponentiation circuit unit in the parallel processor is idle, in response to detecting that the preprocessing circuit unit completes determining the intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold. - View Dependent Claims (9, 10)
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11. A non-transitory storage medium storing one or more programs, the one or more programs when executed by an apparatus, causing the apparatus to perform operations for controlling an RSA decryption processor, wherein the RSA decryption processor comprises a memory, a preprocessing circuit unit and a parallel processor, the memory is configured to store decryption parameters comprising a private key, and a preset first factor and second factor prime with each other, and the operations comprise:
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receiving a ciphertext set; sending a preprocessing signal comprising the ciphertext set to the preprocessing circuit unit, in response to that a ciphertext bit width of the ciphertext set is greater than a predetermined threshold, so that the preprocessing circuit unit reads a decryption parameter from the memory in response to receiving the preprocessing signal, and performs an operation on the decryption parameter and a ciphertext whose bit width is greater than the predetermined threshold in the ciphertext set according to the Chinese remainder theorem, to determine intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold, wherein the intermediate parameters comprise a first base, a first exponent, a second base, and a second exponent;
sending a decryption signal comprising the ciphertext set to the parallel processor in response to that the ciphertext bit width of the ciphertext set is not greater than the predetermined threshold, so that the parallel processor reads a decryption parameter from the memory in response to receiving the decryption signal, and uses at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts;monitoring the preprocessing circuit unit; and determining whether a modular exponentiation circuit unit in the parallel processor is idle, in response to detecting that the preprocessing circuit unit completes determining the intermediate parameters corresponding to the ciphertext whose bit width is greater than the predetermined threshold. - View Dependent Claims (12, 13)
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Specification