Grid array pattern for crosstalk reduction

• US 10,455,690 B1
• Filed: 03/23/2018
• Issued: 10/22/2019
• Est. Priority Date: 03/28/2017
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Chengson, David P., Doppalapudi, Ranjeeth
• Primary Examiner(s): Varghese, Roshn K
• Application Number:
  US15/934,813
• Time in Patent Office: 578 Days
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H05K 1/0215 Grounding of printed circuits by connection to external grounding means
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/10325 Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
• CPC Class Codes: H05K 2201/10719 Land grid array [LGA]
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. The PCB assembly may be used to support a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the PCB assembly. A set of interconnects may be used to intelligently route the first differential signal pair within the package and/or within the PCB. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal and a second interconnect to route the second differential signal toward the particular differential signal.

Claims

1. A printed circuit board (PCB), comprising:

a set of pads associated with facilitating a connection through a package and to a component, wherein the set of pads include a set of via pads and a set of grid array (GA) pads;

a set of vias electrically connected to the set of via pads and to a set of layers that are perpendicular to the set of vias, wherein the set of vias are to be used to support differential signal pairs and are connected to one or more non-ground layers of the set of layers, wherein the differential signal pairs include a first differential signal pair that includes;

a first differential signal that causes crosstalk onto a particular differential signal, of a second differential signal pair, while propagating through the package, and a second differential signal; and

a set of interconnects that electrically connect the set of via pads to the set of GA pads, wherein the set of interconnects include;

a first interconnect to route the first differential signal away from the particular differential signal of the second differential signal pair, and a second interconnect to route the second differential signal toward the particular differential signal, wherein the routed second differential signal causes an amount of crosstalk onto the particular differential signal that is proportional to an amount of crosstalk that the first differential signal causes within the package, and wherein one or more differences in length of the first interconnect with respect to the second interconnect are used to offset one or more differences in a velocity of propagation and cause delay matching of the first and second differential signals.

2. The PCB of claim 1:

wherein a length of the first interconnect and a length of the second interconnect enable the first differential signal and the second differential signal to be delay matched while propagating through the package and the PCB.

3. The PCB of claim 1:

wherein a distance that the first differential signal is to propagate through a package via, of a set of package vias, is a first distance,

wherein another distance that the second differential signal is to propagate through a first PCB via, of the set of PCB vias, is a second distance, and

wherein a length of the first interconnect and a length of the second interconnect is to offset a difference between the first distance and the second distance to enable the first differential signal and the second differential signal to be delay matched.

4. The PCB of claim 1:

wherein a length of the first interconnect and a length of the second interconnect are used to offset differences in a velocity of propagation of the first differential signal and a velocity of propagation of the second differential signal while traveling through a second non-ground layer within the PCB,

wherein the lengths of the first interconnect and the second interconnect cause the first differential signal and the second differential signal to be delay matched while traveling through the package and the PCB.

5. The PCB of claim 1:

wherein a length of the first interconnect or a length of the second interconnect are used to delay match the first differential signal and the second differential signal based on a difference in a diameter of vias used to propagate the first differential signal and the second differential signal.

6. The PCB of claim 1:

wherein the first interconnect and the second interconnect enable crosstalk cancellation as applied to the particular differential signal,

wherein the set of vias includes a set of ground vias that is connected to one or more ground layers of the set of layers, and

wherein a total number of vias, in the set of vias, that are to be used as the set of ground vias, is less than a number of vias that would be used as the set of ground vias if the first interconnect and the second interconnect did not enable crosstalk cancellation.

7. The PCB of claim 1:

wherein the set of vias includes a set of ground vias that is connected to one or more ground layers of the set of layers,

wherein the differential signal pairs that are to be supported by the set of vias are at least 56 gigabytes per second (Gbps) signals, and

wherein each non-ground via, of the set of vias, is adjacent to one ground via, of the set of ground vias.

8. A printed circuit board (PCB) assembly, comprising:

a component that sends or receives differential signal pairs;

a package that is connected to the component; and

a PCB connected to the package, wherein a set of pads are connected to the package or to the PCB to facilitate a connection between the PCB and the component, wherein the set of pads include a set of package via pads, a set of package grid array (GA) pads, a set of PCB via pads, and a set of PCB GA pads, wherein the set of package via pads are connected to a set of package vias, wherein the set of PCB pads are connected to a set of PCB vias, wherein the set of package vias and the set of PCB vias are to be used to support differential signal pairs that include a first differential signal pair, wherein the first differential signal pair includes;

a first differential signal that causes crosstalk onto a particular differential signal, of a second differential signal pair, while propagating through a particular package via, of the set of package vias, and a second differential signal;

wherein a set of interconnects are used to connect package pads to package GA pads or are used to connect PCB pads to PCB GA pads, wherein the set of interconnects includes;

a first interconnect to route the first differential signal away from the particular differential signal, and a second interconnect to route the second differential signal toward the particular differential signal, and wherein one or more differences in length of the first interconnect with respect to the second interconnect are used to offset one or more differences in a velocity of propagation and cause delay matching of the first and second differential signals.

9. The PCB assembly of claim 8:

wherein the first interconnect is located on the package and the second interconnect is located on the PCB, and

wherein routing the second differential signal toward the particular differential signal enables the second differential signal to cause crosstalk onto the particular differential signal,

wherein an amount of crosstalk that the second differential signal causes is proportional to an amount of crosstalk that the first differential signal causes within the particular package via of the set of package vias.

10. The PCB assembly of claim 8:

wherein the first interconnect is located on the PCB and the second interconnect is located on the package, and

wherein routing the second differential signal toward the particular differential signal enables the second differential signal to cause crosstalk onto the particular differential signal,

wherein an amount of crosstalk that the second differential signal causes is proportional to an amount of crosstalk that the first differential signal causes within the particular package via of the set of package vias.

11. The PCB assembly of claim 8, wherein a length of the first interconnect or a length of the second interconnect enable differential signals of the first differential signal pair to be delay matched while propagating through the package and the PCB.

12. The PCB assembly of claim 8:

wherein a length of the first interconnect or a length of the second interconnect are used to delay match the first differential signal and the second differential signal based on at least one of;

a difference in a total distance that the first differential signal and the second differential signal propagate through the package in relation to a total distance that the first differential signal and the second differential signal propagate through the PCB, or

a difference in a velocity of propagation of the first differential signal and the second differential signal while propagating through the package in relation to a velocity of propagation of the first differential signal and the second differential signal while propagating through the PCB.

13. The PCB assembly of claim 8:

wherein the first interconnect and the second interconnect enable crosstalk cancellation as applied to the particular differential signal,

wherein the set of package vias and the set of PCB vias each include a set of ground vias that are connected to one or more ground layers within the package, and the PCB, respectively,

wherein a total number of package vias, in the set of package vias, that are to be used as the set of ground vias, is less than a number of package vias that would be used as the set of ground vias if the set of interconnects did not enable crosstalk cancellation, and

wherein a total number of PCB vias, in the set of PCB vias, that are to be used as the set of ground vias, is less than a number of PCB vias that would be used as the set of ground vias if the set of interconnects did not enable crosstalk cancellation.

14. A package, comprising:

a set of pads associated with facilitating a connection between a printed circuit board (PCB) and one or more components, wherein the set of pads include a set of via pads and a set of grid array (GA) pads;

a set of vias electrically connected to the set of via pads and to a set of layers that are perpendicular to the set of vias, wherein the set of vias are to be used to support differential signal pairs and are connected to one or more non-ground layers of the set of layers, wherein the differential signal pairs include a first differential signal pair that includes;

a first differential signal that causes crosstalk onto a particular differential signal, of a second differential signal pair, while propagating through a particular via, of the set of vias, and a second differential signal; and

a set of interconnects that electrically connect the set of via pads to the set of GA pads, wherein the set of interconnects includes;

a first interconnect to route the first differential signal away from the particular differential signal, a second interconnect to route the second differential signal toward the particular differential signal, and wherein the first interconnect traverses through a non-ground layer and the second interconnect traverses through a different non-ground layer, and wherein one or more differences in length of the first interconnect with respect to the second interconnect are used to offset one or more differences in a velocity of propagation and cause delay matching of the first and second differential signals.

15. The package of claim 14:

wherein routing the second differential signal toward the particular differential signal enables the second differential signal to cause crosstalk onto the particular differential signal,

wherein an amount of crosstalk that the second differential signal causes is proportional to an amount of crosstalk that the first differential signal causes within the particular via of the set of vias.

16. The package of claim 14:

wherein a length of the first interconnect or a length of the second interconnect enable the first differential signal and the second differential signal to be delay matched while propagating through the package and the PCB.

17. The package of claim 14:

wherein a length of the first interconnect or a length of the second interconnect are used to delay match the first differential signal and the second differential signal based on a difference in a total distance that the first differential signal and the second differential signal propagate through the package in relation to a total distance that the first differential signal and the second differential signal propagate through the PCB.

18. The package of claim 14:

wherein a length of the first interconnect or a length of the second interconnect are used to delay match the first differential signal and the second differential signal based on a difference in a velocity of propagation of the first differential signal and the second differential signal while propagating through the package in relation to a velocity of propagation of the first differential signal and the second differential signal while propagating through the PCB.

19. The package of claim 14:

wherein a length of the first interconnect or a length of the second interconnect is used to delay match the first differential signal and the second differential signal based on a difference in a diameter of the particular via in relation to a diameter of a corresponding via in the PCB.

20. The package of claim 14:

wherein the first interconnect and the second interconnect enable crosstalk cancellation as applied to the particular differential signal,

wherein the set of vias includes a set of ground vias that is connected to one or more ground layers of the set of layers, and

wherein a total number of vias, in the set of vias, that are to be used as the set of ground vias, is less than a number of vias that would be used as the set of ground vias if the set of interconnects did not enable crosstalk cancellation.