Grid array pattern for crosstalk reduction

• US 10,455,691 B1
• Filed: 03/23/2018
• Issued: 10/22/2019
• Est. Priority Date: 03/28/2017
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Chengson, David P.
• Primary Examiner(s): Sawyer, Steven T
• Application Number:
  US15/934,826
• Time in Patent Office: 578 Days
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H05K 1/0215 Grounding of printed circuits by connection to external grounding means
• CPC Class Codes: H05K 1/0228 Compensation of cross-talk by a mutually correlated lay-out of printed circuit traces, e.g. for compensation of cross-talk in mounted connectors balanced signal pairs H05K1/0245
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 2201/10325 Sockets, i.e. female type connectors comprising metallic connector elements integrated in, or bonded to a common dielectric support
• CPC Class Codes: H05K 2201/10719 Land grid array [LGA]
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

An apparatus may include via pads and grid array pads associated with facilitating a connection through a package and to a component, and vias that are electrically connected to the via pads, wherein the vias are used to support high-speed differential signal pairs that are capable of causing crosstalk onto other high-speed differential signal pairs while propagating through the package. The apparatus may include interconnects that electrically connect the vias to the grid array pads, and that are capable of routing the high-speed differential signal pairs in a way that offsets the crosstalk that the high-speed differential signal pairs are capable of causing while propagating through the package. The apparatus may include additional interconnects that electrically connect the vias to additional vias that are to be used to facilitate routing the high-speed differential signal pairs to the component, without the high-speed differential signal pairs propagating through a printed circuit board.

Claims

1. A socket, comprising:

a set of pads associated with facilitating a connection through a package and to a component,

wherein the set of pads include a set of via pads and a set of grid array (GA) pads;

a first set of vias that are electrically connected to the set of via pads and that are connected to a set of layers that are perpendicular to the first set of vias,

wherein the first set of vias are to be used to support differential signal pairs,

wherein the differential signal pairs include a first differential signal pair that includes;

a first differential signal that causes crosstalk onto a particular differential signal, of a second differential signal pair, while propagating through the package, and

a second differential signal;

a first set of interconnects that electrically connect the first set of vias to the set of GA pads,

wherein the first set of interconnects include a first interconnect and a second interconnect that route the first differential signal, and the second differential signal, respectively, to offset the crosstalk that the first differential signal causes onto the particular differential signal while propagating through the package; and

a second set of interconnects that electrically connect the first set of vias to a second set of vias that are to be used to facilitate routing the differential signal pairs to the component, without the differential signal pairs propagating through a printed circuit board (PCB),

wherein the first differential signal and the second differential signal are routed to the component through interconnects, of the second set of interconnects, and through vias, of the second set of vias.

2. The socket of claim 1:

wherein the first interconnect routes the first differential signal away from the particular differential signal of the second differential signal pair, and

wherein the second interconnect routes the second differential signal toward the particular differential signal,

wherein the routed second differential signal causes an amount of crosstalk onto the particular differential signal that is proportional to an amount of crosstalk that the first differential signals causes within the package.

3. The socket of claim 1:

wherein the differential signal pairs propagate through the second set of vias to a set of socket fingers that are electrically connected to the second set of vias,

wherein the differential signals propagate through the set of socket fingers to one or more connection mechanisms that are connected to the set of socket fingers,

wherein the differential signals propagate through the one or more connection mechanisms to a set of cables that are connected to the one or more connection mechanisms, and

wherein the differential signals propagate through the set of cables to another socket that is connected to the set of cables,

wherein the other socket is to be used to route the differential signals to the component.

4. The socket of claim 1:

wherein a length of the first interconnect and a length of the second interconnect enable the first differential signal and the second differential signal to be delay matched while propagating through the package and the socket.

5. The socket of claim 1:

wherein a distance that the first differential signal propagates through a package via, of a set of package vias, is a first distance,

wherein another distance that the second differential signal propagates through a first via, of the first set of vias, is a second distance, and

wherein a length of the first interconnect and a length of the second interconnect is to offset a difference between the first distance and the second distance to enable the first differential signal and the second differential signal to be delay matched.

6. The socket of claim 1:

wherein a length of package vias that support the differential signals is a first length,

wherein the differential signal pairs include;

differential signal pairs with signal-to-noise (SNR) ratios in a first range, and

differential signal pairs with signal-to-noise (SNR) ratios in a second range, the second range being lower than the first range,

wherein a first subset of the first set of vias are used to support the differential signal pairs with SNR ratios in the first range,

wherein a length of the first subset of the first set of vias does not satisfy a threshold level of similarity with the first length, and

wherein a second subset of the first set of vias are used to support the differential signal pairs with SNR ratios in the second range,

wherein a length of the second subset of the first set of vias satisfies the threshold level of similarity with the first length.

7. The socket of claim 1:

wherein other signals are routed to the PCB using a third set of vias.

8. A printed circuit board (PCB) assembly, comprising:

a component that sends or receives differential signal pairs,

wherein the differential signal pairs include a first differential signal pair and a second differential signal pair,

wherein the first differential signal pair includes a first differential signal and a second differential signal;

a package electrically connected to the component,

wherein the first differential signal causes crosstalk onto a particular differential signal, of the second differential signal pair, while propagating through the package;

one or more sockets that are electrically connected to the package,

wherein a socket, of the one or more sockets, includes;

a set of pads associated with facilitating connections through the package and to the component,

wherein the set of pads includes a set of via pads and a set of grid array (GA) pads;

a first set of vias that is electrically connected to the set of via pads and that is connected to a set of layers that is perpendicular to the first set of vias,

a first set of interconnects that electrically connect the first set of vias to the set of GA pads,

wherein the first set of interconnects include a first interconnect and a second interconnect that route the first differential signal, and the second differential signal, respectively, to offset the crosstalk that the first differential signal causes onto the particular differential signal while propagating through the package, and

a second set of interconnects that electrically connect the first set of vias to a second set of vias that is to be used to facilitate routing the differential signal pairs to the component, without the differential signal pairs propagating through the PCB; and

a PCB connected to the one or more sockets.

9. The PCB assembly of claim 8:

wherein a length of the first interconnect and a length of the second interconnect enable the first differential signal and the second differential signal to be delay matched while propagating through the package and the socket of the one or more sockets.

10. The PCB assembly of claim 8:

wherein a length of the first interconnect and a length of the second interconnect are used to offset differences in a velocity of propagation of the first differential signal while traveling through the package and a velocity of propagation of the second differential signal while traveling through the socket, and

wherein the length of the first interconnect and the length of the second interconnect are to enable the first differential signal and the second differential signal to be delay matched while traveling through the package and the PCB.

11. The PCB assembly of claim 8:

wherein the differential signal pairs propagate through the second set of vias to a set of socket fingers that is electrically connected to the second set of vias,

wherein a distance between each via, of the second set of vias, is enough to prevent crosstalk from occurring within the second set of vias,

wherein the differential signals propagate through the set of socket fingers to one or more connection mechanisms that are connected to the set of socket fingers,

wherein the differential signals propagate through the one or more connection mechanisms to a set of cables that is connected to the one or more connection mechanisms, and

wherein the differential signals propagate through the set of cables to another socket, of the one or more sockets, that is connected to the set of cables,

wherein the other socket, of the one or more sockets, is to be used to route the differential signals to the component.

12. The PCB assembly of claim 11:

wherein the set of socket fingers do not include socket fingers dedicated to supporting ground signals.

13. An apparatus, comprising:

a set of pads associated with facilitating a connection through a package and to a component,

wherein the set of pads include a set of via pads and a set of grid array (GA) pads;

a first set of vias that is electrically connected to the set of via pads and that is connected to a set of layers that is perpendicular to the first set of vias,

wherein the first set of vias is to be used to support differential signal pairs,

wherein the differential signal pairs cause crosstalk onto other differential signal pairs while propagating through the package;

a first set of interconnects that electrically connect the first set of vias to the set of GA pads,

wherein the first set of interconnects routes the differential signal pairs in a way that offsets the crosstalk that the differential signal pairs cause while propagating through the package; and

a second set of interconnects that electrically connect the first set of vias to a second set of vias that is to be used to facilitate routing the differential signal pairs to the component, without the differential signal pairs propagating through a printed circuit board (PCB).

14. The apparatus of claim 13:

wherein the differential signal pairs include a first differential signal pair that includes;

a first differential signal causes crosstalk onto a particular differential signal, of a second differential signal pair, while propagating through the package, and

a second differential signal,

wherein the first set of interconnects include a first interconnect that the first differential signal away from the particular differential signal of the second differential signal pair, and

wherein the first set of interconnects include a second interconnect that routes the second differential signal toward the particular differential signal,

wherein the routed second differential signal causes an amount of crosstalk onto the particular differential signal that is proportional to an amount of crosstalk that the first differential signal causes within the package.

15. The apparatus of claim 13:

wherein the first set of interconnects are of a length that delay matches a time needed for the differential signal pairs to propagate through the package with a time needed for the differential signal pairs to propagate through the apparatus.

16. The apparatus of claim 13:

wherein the first set of interconnects are of a length that is used to delay match the differential signal pairs, and

wherein the length is based on a difference in a diameter of package vias used to propagate the differential signal pairs in the package and a diameter of the first set of vias used to propagate the differential signal pairs in the apparatus.

17. The apparatus of claim 13:

wherein the first set of interconnects are of a length that is used to delay match the differential signal pairs, and

wherein the length is based on a velocity of propagation of the differential signal pairs while propagating through the package in relation to a velocity of propagation of the differential signal pairs while propagating through the apparatus.

18. The apparatus of claim 13:

wherein the differential signals propagate through the second set of vias to a set of socket fingers that is electrically connected to the second set of vias,

wherein a distance between each via, of the second set of vias, is based on a signal speed of the differential signals, and is enough distance to prevent crosstalk from occurring within the second set of vias,

wherein the differential signals propagate through the set of socket fingers to one or more connection mechanisms that are connected to the set of socket fingers,

wherein the differential signals propagate through the one or more connection mechanisms to a set of cables that is connected to the one or more connection mechanisms, and

wherein the differential signals propagate through the set of cables to a backplane connector that is connected to the set of cables,

wherein the backplane connector is to be used to route the differential signals to the component.

19. The apparatus of claim 13:

wherein a length of package vias that support propagation of the differential signal pairs through the package is a first length,

wherein the differential signal pairs include;

differential signal pairs with signal-to-noise (SNR) ratios in a first range, and

differential signal pairs with signal-to-noise (SNR) ratios in a second range, the second range being lower than the first range,

wherein a first subset of the first set of vias is to be used to support the differential signal pairs with SNR ratios in the first range,

wherein a length of the first subset of the first set of vias does not satisfy a threshold level of similarity with the first length, and

wherein a second subset of the first set of vias is to be used to support the differential signal pairs with SNR ratios in the second range,

wherein a length of the second subset of the first set of vias satisfies the threshold level of similarity with the first length.

20. The apparatus of claim 13:

wherein other signals are routed to the PCB using a third set of vias.