Configurable computing array comprising configurable computing elements

• US 10,456,800 B2
• Filed: 09/05/2018
• Issued: 10/29/2019
• Est. Priority Date: 03/05/2016
• Status: Active Grant

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Tran, Anh Q
• Application Number:
  US16/121,653
• Publication Number:
  US 20180361411A1
• Time in Patent Office: 419 Days
• Field of Search: 326 37- 47
• CPC Class Codes: B05B 11/0064 Lift valves B05B11/007 takes precedence
• CPC Class Codes: B05B 11/0072 A valve member forming part of an outlet opening
• CPC Class Codes: B05B 11/047 characterised by the outlet or venting means B05B11/041 and B05B11/042 take precedence
• CPC Class Codes: B05B 11/1022 actuated by pressure
• CPC Class Codes: B05B 11/1073 Springs
• CPC Class Codes: B05B 11/1097 with means for sucking back the liquid or other fluent material in the nozzle after a dispensing stroke
• CPC Class Codes: B65D 47/0838 located at an edge of the base element
• CPC Class Codes: B65D 47/2068 in which the stem is lowered by the pressure of the contents and thereby opening the valve
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

To implement a complex math function, i.e. a math function with multiple input variables, a configurable computing array comprises at least an array of configurable computing elements. Each configurable computing element comprises at least a memory which stores a look-up table (LUT) for a math function with a single input variable.

Claims

1. A configurable computing array, comprising:

at least an array of configurable logic elements including a configurable logic element for selectively realizing a logic function from a logic library; and

at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises at least a first memory for storing at least a first portion of a first look-up table (LUT) for a first math function; and

, said second configurable computing element comprises at least a second memory for storing at least a second portion of a second LUT for a second math function;

whereby said configurable computing array realizes a third math function by programming said configurable logic elements and said configurable computing elements, wherein said third math function is a combination of at least said first and second math functions;

wherein each of said first and second math functions includes more operations than arithmetic operations included in said logic library.

2. The configurable computing array according to claim 1, wherein said arithmetic operations included in said logic library consist of arithmetic addition and arithmetic subtraction.

3. The configurable computing array according to claim 1, wherein said first math function has a first independent variable;

said second math function has a second independent variable; and

, said third math function has at least said first and second independent variables.

4. The configurable computing array according to claim 1, further comprising a plurality of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

5. The configurable computing array according to claim 1, wherein said first or second memory includes a three-dimensional memory (3D-M) array formed above said configurable logic element.

6. The configurable computing array according to claim 5, wherein said 3D-M array at least partially covers said configurable logic element.

7. The configurable computing array according to claim 1, wherein said first and second memories are electrically re-programmable, whereby said configurable computing elements can be re-configured to realize different math functions.

8. The configurable computing array according to claim 1, wherein said array of configurable logic elements and said array of configurable computing elements are disposed on different physical levels.

9. The configurable computing array according to claim 8, wherein said first or second memory at least partially overlaps with said configurable logic element.

10. The configurable computing array according to claim 1, further comprising at least one multiplier.

11. A configurable computing array, comprising:

at least an array of configurable logic elements including a configurable logic element for selectively realizing a logic function from a logic library; and

at least an array of configurable computing elements including first and second configurable computing elements, wherein said first configurable computing element comprises at least a first re-programmable memory for storing at least a first portion of a first look-up table (LUT) for a first math function; and

, said second configurable computing element comprises at least a second re-programmable memory for storing at least a second portion of a second LUT for a second math function;

whereby said configurable computing array realizes a third math function by programming said configurable logic elements and said configurable computing elements, wherein said third math function is a combination of at least said first and second math functions;

wherein each of said first and second math functions includes more operations than arithmetic operations included in said logic library.

12. The configurable computing array according to claim 11, wherein said arithmetic operations included in said logic library consist of arithmetic addition and arithmetic subtraction.

13. The configurable computing array according to claim 11, wherein said first math function has a first independent variable;

said second math function has a second independent variable; and

, said third math function has at least said first and second independent variables.

14. The configurable computing array according to claim 11, further comprising a plurality of configurable interconnects including a configurable interconnect, wherein said configurable interconnect selectively realizes an interconnect from an interconnect library.

15. The configurable computing array according to claim 11, wherein said first or second memory includes a three-dimensional memory (3D-M) array formed above said configurable logic element.

16. The configurable computing array according to claim 15, wherein said 3D-M array at least partially covers said configurable logic element.

17. The configurable computing array according to claim 11, wherein said array of configurable logic elements and said array of configurable computing elements are disposed on different physical levels.

18. The configurable computing array according to claim 17, wherein said first memory and said configurable logic element at least partially overlap.

19. The configurable computing array according to claim 17, wherein said second memory and said configurable logic element at least partially overlap.

20. The configurable computing array according to claim 11, further comprising at least one multiplier.