Low flux and low noise detection circuit

• US 10,458,842 B2
• Filed: 11/20/2017
• Issued: 10/29/2019
• Est. Priority Date: 11/21/2016
• Status: Active Grant

• Current Assignee: Societe Francaise de Detecteurs Infrarouges-Sofradir
• Original Assignee: Societe Francaise de Detecteurs Infrarouges-Sofradir
• Inventors: Sanson, Eric, Aufranc, Sebastien
• Primary Examiner(s): Ko, Tony
• Application Number:
  US15/818,220
• Publication Number:
  US 20180143072A1
• Time in Patent Office: 708 Days
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01J 5/22 Electrical features thereof
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 5/33 Transforming infrared radiation cameras or camera modules for generating image signals from infrared radiation H04N23/20; circuitry of SSIS for transforming infrared radiation into image signals H04N25/20

Abstract

The detection circuit comprises a detector connected to an integration node. A bias circuit biases the detector between a first bias state and a second floating state. The potential of the integration node is at a target value when the bias circuit biases the detector to the first state and varies when the detector is in floating state. A measurement circuit without charge losses delivers a value representative of the potential present on the integration node N. A transfer circuit of the electric charges performs transfer of the electric charges from a stray capacitor of the photodiode to an integration capacitor. An output terminal delivers a voltage representative of the potential present on the second terminal of the first capacitor.

Claims

1. Detection circuit comprising:

a detector having a stray capacitor, the detector being configured to deliver electric charges according to an observed phenomenon,

a bias circuit configured to bias the detector during a first period and to leave a first terminal of the detector at a floating potential during a second period,

a first capacitor having a first terminal connected to the first terminal of the detector to form an integration node with the stray capacitor, the integration node being at a potential target value during the first period and at a changing potential during the second period,

a transfer circuit configured to transfer electric charges from the stray capacitor to the first capacitor, the transfer circuit being configured to bias a second terminal of the first capacitor so as to shift a potential of the integration node to the potential target value for transferring the electric charges and to disable transfer of the electric charges when the potential of the integration node reaches a predefined value,

an output terminal delivering a voltage representative of the potential present on the second terminal of the first capacitor.

2. Circuit according to claim 1, comprising a measurement circuit configured to measure the potential of the integration node and wherein the measurement circuit delivers data representative of the potential of the integration node to the transfer circuit so that the transfer circuit delivers a voltage configured to transfer the electric charges from the stray capacitor to the first capacitor.

3. Circuit according to claim 2, wherein the measurement circuit comprises a follower transistor having a control electrode connected to the integration node so as to modulate a voltage delivered by the follower transistor according to the potential of the integration node.

4. Circuit according to claim 3, wherein an output of the follower transistor is connected to the transfer circuit and configured so that transfer of the electric charges from the stray capacitor to the first capacitor is stopped when the follower transistor delivers a voltage representative of the predefined value.

5. Circuit according to claim 2, wherein the transfer circuit comprises an amplifier receiving a value representative of the potential of the integration node on a first input, and a value representative of the predefined value on a second input, an output of the amplifier being connected to apply a voltage on the second terminal of the first capacitor.

6. Circuit according to claim 5, wherein the amplifier is formed by an operational amplifier and an output of the operational amplifier supplies voltage to the second terminal of the first capacitor.

7. Circuit according to claim 6, wherein the bias circuit applies a first voltage value to the first terminal of the detector during the first period and wherein the operational amplifier receives on a first input a voltage offset from said first voltage value by a value equal to a threshold voltage of a transistor connected as follower transistor.

8. Circuit according to claim 1, comprising a second capacitor having a first terminal connected to the second terminal of the first capacitor and a second terminal connected to a second voltage source delivering a fixed potential.

9. Circuit according to claim 1, comprising a transfer switch configured to enable or disable a flow of electric charges between the second terminal of the first capacitor and the transfer circuit.

10. Circuit according to claim 1, comprising a measurement switch connected between the measurement circuit and the transfer circuit.

11. Circuit according to claim 10, wherein the measurement switch and/or the transfer switch are formed by a field effect transistor.

12. Circuit according to claim 10, wherein the transfer switch and the measurement switch receive a same synchronisation signal on their control electrode.

13. Circuit according to claim 9, comprising a control circuit configured to activate the transfer circuit at least twice during the second period, the control circuit being configured to disable charge transfer between two consecutive activation phases of the transfer circuit.

14. Circuit according to claim 13, wherein the control circuit is configured to switch the transfer switch to off state between the two consecutive activation phases of the transfer circuit.

15. Detection matrix comprising a plurality of detection circuits according to claim 1 organised in rows and in columns.

16. Detection matrix according to claim 15, wherein the bias circuits of the detection circuits receive a same first synchronisation signal.

17. Detection matrix according to claim 15, characterized in that a transfer circuit is common to a plurality of detection circuits.

18. Detection matrix according to claim 17, wherein the bias circuits of a row or of a column of detection circuits are connected to a control circuit configured to perform simultaneous switching between the first period and second period and wherein the control circuit and transfer circuit are configured to perform transfer of the electric charges from the integration nodes of said detection circuits sequentially during the second period.