Semiconductor test apparatus for testing semiconductor devices

• US 10,459,027 B2
• Filed: 03/31/2015
• Issued: 10/29/2019
• Est. Priority Date: 03/31/2015
• Status: Active Grant

• Current Assignee: Unitechno Inc.
• Original Assignee: Unitechno Inc.
• Inventors: Adachi, Tomoaki, Yamada, Munehiro
• Primary Examiner(s): Tang, Minh N
• Application Number:
  US15/562,821
• Publication Number:
  US 20180106860A1
• Time in Patent Office: 1,673 Days
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/26 Testing of individual semiconductor devices testing or measuring during manufacture or treatment H01L22/00; testing of photovoltaic devices H02S50/10
• CPC Class Codes: G01R 31/2893 Handling, conveying or loading, e.g. belts, boats, vacuum fingers G01R31/2867 takes precedence; handling semiconductor devices or wafers during manufacture or treatment H01L21/67

Abstract

A semiconductor test apparatus capable of securely having the contact pin and the external contact terminal held in contact with each other even in case where the vertical type handler is used. The semiconductor test apparatus comprises: a test socket having a socket surface formed thereon, the socket surface having a contact pin towering therefrom; and a semiconductor transport fixture having a concave portion formed thereon, the concave portion adapted to receive therein an IC under test, wherein the test socket has a position adjustment guide provided thereon, the semiconductor transport fixture has a guide through bore formed therein, the guide through bore adapted to receive the position adjustment guide therethrough when the IC under test comes under test, and either one of the position adjustment guide or the guide through bore is formed in a tapered shape.

Claims

1. A semiconductor test apparatus, comprising:

a test socket having a socket surface formed thereon, the socket surface having a contact pin towering therefrom; and

a semiconductor transport fixture having a concave portion formed thereon, the concave portion adapted to receive therein an IC under test, wherein

the test socket has a position adjustment guide provided thereon,

the semiconductor transport fixture has a guide through bore formed therein, the guide through bore adapted to receive the position adjustment guide therethrough when the IC under test comes under test, and

either one of the position adjustment guide or the guide through bore is formed in a tapered shape such that, when the guide through bore receives therethrough the position adjustment guide at the time of test of the IC under test, the position adjustment guide pushes upward the IC under test to adjust the position of the IC under test.

2. The semiconductor test apparatus as set forth in claim 1, wherein

the position adjustment guide is fixed to perpendicularly tower from the socket surface, and

the position adjustment guide is formed in a tapered shape approaching the contact pin as advancing in a longitudinal direction from a tip toward a base thereof.

3. The semiconductor test apparatus as set forth in claim 1, wherein

the position adjustment guide is rotatably supported by a hinge mechanism arranged on the test socket,

the position adjustment guide is so urged to perpendicularly tower from the socket surface, and

the guide through bore is formed in a tapered shape approaching the concave portion as advancing toward inside thereof.

4. The semiconductor test apparatus as set forth in claim 3, wherein

the position adjustment guide has a small protrusion provided on an upper side thereof.

5. The semiconductor test apparatus as set forth in claim 1, wherein

the test socket has a lateral position adjustment guide further provided respectively in a right end portion and a left end portion on the socket surface, each of the lateral position adjustment guides towering perpendicularly from the socket surface,

the guide through bore is adapted to receive the lateral position adjustment guide therethrough when the IC under test comes under test, and

either one of the lateral position adjustment guide or the guide through bore is formed in a tapered shape.

6. The semiconductor test apparatus as set forth in claim 1, wherein

the test socket includes a plurality of the contact pins and a positioning base, the positioning base being located among the neighboring plurality of contact pins, the positioning base being urged to be at a position more spaced apart from the socket surface than a tip of the contact pin.