Measuring internal signals of an integrated circuit

• US 10,459,030 B2
• Filed: 10/19/2017
• Issued: 10/29/2019
• Est. Priority Date: 02/11/2016
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Murthy, Kushal D, Parmar, Manish, Tadeparthy, Preetam, Venkateswaran, Muthusubramanian
• Primary Examiner(s): McMahon, Daniel F.
• Application Number:
  US15/788,292
• Publication Number:
  US 20180038913A1
• Time in Patent Office: 740 Days
• Field of Search: None
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.

Claims

1. A device comprising:

an interface pin;

one or more blocks of circuitry;

a multiplexor having inputs and an output;

signal lines coupled from the one or more blocks of circuitry to the inputs on the multiplexor;

a first buffer having;

a first input coupled to the output of the multiplexor; and

a first output selectively connected to the interface pin;

a second buffer having;

a second input coupled to the output of the multiplexor; and

a second output selectively connected to the interface pin; and

a switch configured to bypass the first and second buffers by selectively connecting the output of the multiplexor directly to the interface pin;

the first buffer being a PMOS source follower, and the second buffer being an NMOS source follower.

2. The device of claim 1, wherein the interface pin is a first interface pin, and the device further comprises a second interface pin coupled to one of the inputs of the multiplexor.

3. The device of claim 1, wherein the first buffer is a unity gain buffer.

7. The device of claim 1, wherein the PMOS source follower is configured to buffer signals having an amplitude in a range of a first threshold value to a ground reference value, and the NMOS source follower is configured to buffer signals having an amplitude in a range of a second threshold value to a supply reference value.

8. The device of claim 1, wherein the interface pin is a first interface pin, and the device further comprises a second interface pin coupled to the multiplexor and the switch.

4. An integrated circuit (IC) comprising:

an interface pin;

functional logic having signal lines; and

test logic having;

inputs coupled to the signal lines; and

an output coupled to the interface pin, in which the test logic includes first and second buffers, and the test logic is configured to selectively connect any of the signal lines either directly or via one of the first and second buffers to the interface pin;

the first buffer being a PMOS source follower, and the second buffer being an NMOS source follower.

5. The IC of claim 4, wherein the interface pin is a first interface pin, and the integrated circuit further comprises a second interface pin coupled to an input of the test logic, in which the test logic is configured to selectively connect the second interface pin via one of the first and second buffers to the first interface pin.

6. The IC of claim 4, wherein the first buffer is a unity gain buffer.

9. The IC of claim 4, wherein the interface pin is a first interface pin, and the IC further comprises a second interface pin coupled to the test logic.

10. The IC of claim 4, wherein the PMOS source follower is configured to buffer signals having an amplitude in a range of a first threshold value to a ground reference value, and the NMOS source follower is configured to buffer signals having an amplitude in a range of a second threshold value to a supply reference value.