Measuring internal signals of an integrated circuit
First Claim
1. A device comprising:
- an interface pin;
one or more blocks of circuitry;
a multiplexor having inputs and an output;
signal lines coupled from the one or more blocks of circuitry to the inputs on the multiplexor;
a first buffer having;
a first input coupled to the output of the multiplexor; and
a first output selectively connected to the interface pin;
a second buffer having;
a second input coupled to the output of the multiplexor; and
a second output selectively connected to the interface pin; and
a switch configured to bypass the first and second buffers by selectively connecting the output of the multiplexor directly to the interface pin;
the first buffer being a PMOS source follower, and the second buffer being an NMOS source follower.
0 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit (IC) is provided with functional logic having a plurality of internal signal lines and test logic. The test logic has a plurality of inputs coupled to the plurality of internal signal lines and with an output coupled to a first external pin of the integrated circuit. The test logic includes a buffer, and the test logic is configured to selectively couple each of the signals received on the plurality of signal lines either directly or via the buffer to the first external pin of the IC. The test logic is configured to selectively couple a signal received on a second external pin of the IC either directly or via the buffer to the first external pin of the IC in order to calibrate the buffer.
8 Citations
10 Claims
-
1. A device comprising:
-
an interface pin; one or more blocks of circuitry; a multiplexor having inputs and an output; signal lines coupled from the one or more blocks of circuitry to the inputs on the multiplexor; a first buffer having;
a first input coupled to the output of the multiplexor; and
a first output selectively connected to the interface pin;a second buffer having;
a second input coupled to the output of the multiplexor; and
a second output selectively connected to the interface pin; anda switch configured to bypass the first and second buffers by selectively connecting the output of the multiplexor directly to the interface pin; the first buffer being a PMOS source follower, and the second buffer being an NMOS source follower. - View Dependent Claims (2, 3, 7, 8)
-
-
4. An integrated circuit (IC) comprising:
-
an interface pin; functional logic having signal lines; and test logic having;
inputs coupled to the signal lines; and
an output coupled to the interface pin, in which the test logic includes first and second buffers, and the test logic is configured to selectively connect any of the signal lines either directly or via one of the first and second buffers to the interface pin;the first buffer being a PMOS source follower, and the second buffer being an NMOS source follower. - View Dependent Claims (5, 6, 9, 10)
-
Specification