Semiconductor device

• US 10,459,162 B2
• Filed: 07/16/2018
• Issued: 10/29/2019
• Est. Priority Date: 09/05/2017
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Iida, Tetsuya, Nakashiba, Yasutaka
• Primary Examiner(s): Lepisto, Ryan A
• Application Number:
  US16/036,455
• Publication Number:
  US 20190072717A1
• Time in Patent Office: 470 Days
• CPC Class Codes: G02B 2006/12061 Silicon
• CPC Class Codes: G02B 2006/12119 Bend
• CPC Class Codes: G02B 6/1228 Tapered waveguides, e.g. integrated spot-size transformers for coupling with fibres G02B6/305
• CPC Class Codes: G02B 6/125 Bends, branchings or intersections

Abstract

To provide a semiconductor device including a low-loss optical waveguide. The optical waveguide included in the semiconductor device has a core layer covered with first and second clad layers having respectively different refractive indices. A portion of the core layer is covered at a first ratio, that is, a ratio of the first clad layer to the second clad layer and at the same time, a second ratio, that is, a ratio of the second clad layer to the first clad layer. At this time, the first ratio and the second ratio are each a finite value more than 0.

Claims

1. A semiconductor device, comprising:

a core layer,

a first clad layer having a refractive index lower than that of the core layer, and

a second clad layer having a refractive index lower than that of the core layer and different from that of the first clad layer,

the core layer comprising;

a first portion contacting with the first clad layer and overlapping with the first clad layer in a plan view;

a second portion comprising;

a first overlapping portion contacting with the first clad layer and overlapping with the first clad layer in the plan view; and

a second overlapping portion contacting with the second clad layer and overlapping with the second clad layer in the plan view, the second overlapping portion being adjacent to the first portion; and

a third portion contacting with the second clad layer and overlapping with the second clad layer in the plan view, the third portion being adjacent to the second portion and having a finite radius of curvature,

wherein, in a cross-section orthogonal to an extending direction of the second portion and passing through the second portion, a first ratio of a first contact area of an upper surface of the core layer and the first clad layer to a second contact area of the upper surface of the core layer and the second clad layer, and a second ratio of a third contact area of the upper surface of the core layer and the second clad layer to a fourth area of the core layer and the first clad layer are each a finite value more than 0,

wherein the first ratio, in the cross-section orthogonal to the extending direction of the second portion and passing through the second portion, is lower than the first ratio in a cross-section orthogonal to an extending direction of the first portion and passing through the first portion, and is greater than the first ratio in a cross-section orthogonal to an extending direction of the third portion and passing through the third portion, and

wherein the second ratio, in the cross-section orthogonal to the extending direction of the second portion and passing through the second portion, is greater than the second ratio in the cross-section orthogonal to an extending direction of the first portion and passing through the first portion, and is lower than the second ratio in a cross-section orthogonal to an extending direction of the third portion and passing through the third portion.

2. The semiconductor device according to claim 1, wherein the first ratio, in a first cross-section orthogonal to ti extending direction of the second portion, passing through the second portion and located on a side of the first portion, is greater than the first ratio in a second cross-section orthogonal to the extending direction of the second portion and passing through the second portion, and located on a side closer to the third portion than the first cross-section.

3. The semiconductor device according to claim 1, wherein the second ratio at a position in which each of the first clad layer and the second clad layer contacts with the core layer in a first cross-section orthogonal to the extending direction of the second portion and passing through the second portion, and located on a side of the first portion, is lower than the second ratio at a position in which each of the first clad layer and the second clad layer contacts with the core layer in a second cross-section orthogonal to the extending direction of the second portion and passing through the second portion, and located on a side closer to the third portion than the first cross-section.

4. The semiconductor device according to claim 1, wherein the first ratio decreases as going from a first cross-section orthogonal to the extending direction of the second portion and passing through the second portion, and located on a side of the first portion to a second cross-section orthogonal to the extending direction of the second portion, passing through the second portion, and located on a side closer to the third portion than the first cross-section.

5. The semiconductor device according to claim 1, wherein the second ratio increases as going from a first cross-section orthogonal to the extending direction of the second portion, passing through the second portion, and located on a side of the first portion to a second cross-section orthogonal to the extending direction of the second portion, passing through the second portion, and located on a side closer to the third portion than the first cross-section.

6. The semiconductor device according to claim 1, wherein the second portion includes a portion extending in a first direction.

7. The semiconductor device according to claim 1, wherein the second portion includes a portion extending in a first direction and a portion having a finite radius of curvature.

8. The semiconductor device according to claim 1, wherein the second portion includes a portion having a finite radius of curvature.

9. The semiconductor device according to claim 1, wherein a planar shape of the first overlapping portion includes a taper shape.

10. The semiconductor device according to claim 1, wherein a planar shape of the first overlapping portion includes a rugged shape.

11. The semiconductor device according to claim 1, wherein a planar shape of a tip portion of the first overlapping portion includes an arc shape.

12. The semiconductor device according to claim 1, wherein the first portion has a rectangular planar shape.

13. The semiconductor device according to claim 1, wherein the third portion has a planar shape same as that of a U-shaped curved portion.

14. The semiconductor device according to claim 1, wherein the second portion includes an upper surface, a first side surface crossing the upper surface, and a second side surface opposite to the first side surface,

wherein the upper surface of the second portion is covered with the first clad layer and the second clad layer,

wherein the first side surface of the second portion is covered with the first clad layer or the second clad layer, and

wherein the second side surface of the second portion is covered with the first clad layer or the second clad layer.

15. The semiconductor device according to claim 1, wherein the semiconductor device includes a silicon on insulator (SOI) substrate,

wherein the SOI substrate comprises:

a support substrate;

a buried insulating layer formed over the support substrate; and

a semiconductor layer formed over the buried insulating layer, and

wherein the core layer includes the semiconductor layer.

16. The semiconductor device according to claim 15, wherein the buried insulating layer comprises:

an overlapping portion with the core layer in the plan view; and

a non-overlapping portion with the core layer in the plan view, and

wherein both a portion of the overlapping portion and a portion of the non-overlapping portion have an impurity introduced therein, for changing a refractive index of the buried insulating layer.

17. The semiconductor device according to claim 16, wherein a refractive index of a region including a portion of the overlapping portion and a portion of the non-overlapping portion of the buried insulating layer formed right below the first portion of the core layer and having a first impurity introduced therein is greater than a refractive index of a region including a portion of the overlapping portion and a portion of the non-overlapping portion of the buried insulating layer formed right below the third portion of the core layer and having a second impurity introduced therein, the second impurity being different from the first impurity.

18. The semiconductor device according to claim 15, wherein the buried insulating layer comprises:

an overlapping portion with the core layer in the plan view; and

a non-overlapping portion with the core layer in the plan view, and

wherein the overlapping portion has an impurity introduced therein for changing a refractive index of the buried insulating layer.

19. The semiconductor device according to claim 1, wherein the first clad layer comprises a SiON film, and

wherein the second clad layer comprises a SiOF film.