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Touch display pane and display device

  • US 10,459,556 B2
  • Filed: 08/17/2017
  • Issued: 10/29/2019
  • Est. Priority Date: 07/20/2017
  • Status: Active Grant
First Claim
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1. A touch display panel, comprising:

  • a first substrate defined with a display region and a non-display region;

    a second substrate disposed opposite to the first substrate, wherein the first substrate is an upper substrate relative to the second substrate, and the second substrate is a lower substrate relative to the first substrate;

    a first solder pad;

    a second solder pad; and

    a touch sensing layer disposed on a side of the first substrate away from the second substrate;

    wherein, the first solder pad and the second solder pad are disposed at the non-display region of the first substrate, the first solder pad is connected to a touch control circuit, and the second solder pad is connected to a display driving circuit; and

    wherein, the first solder pad and the second solder pad are disposed at a solder region of the first substrate that is in parallel with the non-display region and next to a boundary of the display region, a width of the solder region measured closest to the boundary and farthest away from the boundary is less than a sum of a width of the first solder pad and a width of the second solder pad;

    wherein the first solder pad and the second solder pad are disposed on the first substrate;

    wherein, the first solder pad and the second solder pad are disposed oppositely at two sides of the non-display region of the first substrate;

    wherein, the first substrate comprises;

    a black masking layer;

    a semiconductor active layer;

    a gate electrode;

    a drain electrode; and

    a source electrode;

    wherein the gate electrode, the drain electrode and the source electrode are covered by the semiconductor active layer;

    wherein the semiconductor active layer is fully covered by the black masking layer;

    wherein a projected area of the semiconductor active layer is less than a total projected area of the gate electrode, the drain electrode and the source electrode.

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