Memory systems, modules, and methods for improved capacity

• US 10,459,660 B2
• Filed: 11/04/2015
• Issued: 10/29/2019
• Est. Priority Date: 11/20/2014
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Best, Scott C.
• Primary Examiner(s): Tran, Uyen B
• Application Number:
  US15/522,164
• Publication Number:
  US 20170337014A1
• Time in Patent Office: 1,455 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

Claims

1. A memory system comprising:

a controller component to issue memory commands and communicate data via a controller interface; and

memory modules, including a first memory module and a second memory module, each memory module having;

a module data interface connected to the controller interface via passive point-to-point data connections that extend from the module data interface to the controller interface, the passive point-to-point data connections to communicate a subset of the data;

at least one delay-configurable data buffer coupled to the module data interface to communicate the subset of the data;

memory devices coupled to the at least one delay-configurable data buffer to store and convey the subset of the data;

a command input port connected to the controller interface via a command connection separate from the passive point-to-point data connections, the command input port to receive the memory commands from the controller component;

a command output port;

a command relay circuit coupled between the command input port and the command output port, the command relay circuit to relay the memory commands received from the controller component away from the memory module on the command output port; and

command logic coupled to the command input port to receive the memory commands from the controller component, the command logic to issue device commands to the memory devices responsive to the memory commands.

2. The memory system of claim 1, further comprising passive point-to-point connections that extend from the command output port of the first memory module to the command input port of the second memory module.

3. The memory system of claim 2, further comprising passive point-to-point connections that extend from the controller interface and to command input port of the first memory module.

4. The memory system of claim 3, wherein the delay-configurable data buffer of the first memory module is configured to impose a first data delay and the delay-configurable data buffer of the second memory module is configured to impose a second data delay less than the first data delay.

5. The memory system of claim 4, wherein the command relay circuit of the first memory module imposes a relay delay equal to the first data delay.

6. The memory system of claim 4, wherein the delay-configurable data buffer is configured to impose the first data delay on read-data signals and write-data signals.

7. The memory system of claim 1, wherein the at least one delay-configurable data buffer includes switching logic to programmably direct data from different subsets of the memory devices to the module data interface.

8. The memory system of claim 1, further comprising a passive point-to-point connection extending from the command relay circuit of the first memory module to the command input port of the second memory module.

9. The memory system of claim 1, each memory module further comprising a register to store a register value indicative of a delay through the delay-configurable data buffer.

10. A memory module comprising:

a module data interface to communicate data signals external to the memory module;

at least one delay-configurable data buffer coupled to the module data interface to selectively delay the data signals;

memory devices coupled to the at least one delay-configurable data buffer to store and convey the selectively delayed data signals;

a command input port separate from the module data interface, the command input port to receive memory commands from a controller component;

a command output port;

a command relay circuit coupled between the command input port and the command output port to convey the memory commands from the memory module; and

command logic coupled to the command input port to receive the memory commands from the controller component, the command logic to issue commands to the memory devices responsive to the memory commands;

wherein the delay-configurable data buffer is configured to impose a first data delay and the command relay circuit imposes a relay delay equal to the first data delay.

11. The memory module of claim 10, wherein the at least one delay-configurable data buffer includes switching logic to programmably direct data from different subsets of the memory devices to the module data interface.

12. The memory module of claim 10, further comprising a register to store a register value indicative of a delay through the delay-configurable data buffer.

13. The memory module of claim 10, wherein the at least one delay-configurable data buffer is configured to impose a read delay on read-data signals and a write delay on write-data signals.

14. The memory module of claim 13, wherein the read delay equals the write delay.

15. A method of communicating with first memory devices on a first memory module and second memory devices on a second memory module, the method comprising:

issuing a command to the first memory module;

delaying the command on the first memory module by a delay to produce a first delayed command;

relaying the command through the first memory module to the second memory module, the relaying introducing the delay in the command to produce a second delayed command;

issuing the first delayed command to the first memory devices on the first memory module; and

issuing the second delayed command to the second memory devices on the second memory module.

16. The method of claim 15, wherein the delay is one clock cycle.

17. The method of claim 15, further comprising buffering write data to the first memory devices and the second memory devices to introduce the delay in the write data.

18. The method of claim 17, further comprising configuring the first memory module and the second memory module to introduce the delay in the write data.

19. The method of claim 18, wherein configuring the first memory module and the second memory module comprises writing a first configuration value to the first memory module and a second configuration value different from the first configuration value to the second memory module.