Write failure handling for a memory controller to non-volatile memory

• US 10,459,662 B1
• Filed: 09/27/2017
• Issued: 10/29/2019
• Est. Priority Date: 09/27/2017
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Volpe, Thomas A., Banse, Mark Anthony, Larson, Steven Scott
• Primary Examiner(s): Peugh, Brian R
• Application Number:
  US15/717,759
• Time in Patent Office: 762 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/657 Virtual address space management
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

Failed write handling can be implemented at a memory controller for non-volatile memory. Failure of a write to a storage location in the non-volatile memory may be detected. An indication of the failure may be sent to a microcontroller for the non-volatile memory which may return an instruction to write to a different location in the non-volatile memory. Reads and writes to the storage location of the failed write may still be allowed, in some embodiments, by redirecting the reads and writes to a copy of data of the failed write stored in a copy buffer in the memory controller.

Claims

1. A system, comprising:

an access device for a non-volatile memory that provides a host processor with access to the non-volatile memory, the access device comprising a microcontroller and a memory controller;

wherein the memory controller is configured to;

receive a request to write data to a storage location in the non-volatile memory from the host processor;

send a command to the non-volatile memory device to write the data to the storage location in the non-volatile memory;

evaluate a command result to determine that the write to the storage location in the non-volatile memory failed;

send an interrupt indicating the failed write to the storage location to the microcontroller;

receive a request to write the data to a different storage location in the non-volatile memory from the microcontroller; and

send another command to the non-volatile memory device to write the data to the different storage location in the non-volatile memory.

2. The system of claim 1, wherein the memory controller comprises a copy buffer and wherein the memory controller is further configured to:

in response to the determination that the write to the storage location in the non-volatile memory failed;

identify an entry in the copy buffer for the data; and

store the data in the entry in the copy buffer;

wherein the request to write the data to the different storage location is a request to copy the data from the entry in the copy buffer to the different storage location.

3. The system of claim 2, wherein the memory controller is further configured to:

before the request to write the data to the different storage location is received;

receive a request to read the storage location;

read the entry of the copy buffer to obtain the data; and

return the data read from the copy buffer in response to the request to read the storage location.

4. The system of claim 1, wherein the non-volatile memory is a storage class memory device.

5. A method, comprising:

detecting, by a memory controller for a non-volatile memory, a failure of a write of data to a storage location in the non-volatile memory;

sending, by the memory controller, an indication of the failed write to the storage location to a microcontroller for the non-volatile memory;

receiving, at the memory controller, a request to write the data to a different storage location in the non-volatile memory from the microcontroller; and

performing, by the memory controller, the write of the data to the different storage location in the non-volatile memory.

6. The method of claim 5, wherein the failed write was a write to copy the data from an entry of a copy buffer to the storage location and wherein the sending the indication of the failed write comprises modifying a migration status for the entry of the copy buffer to indicate a failure of the write.

7. The method of claim 5, further comprising:

in response to detecting the failure of the write of data to the storage location in the non-volatile memory;

identifying an entry in the copy buffer for the data; and

storing the data in the entry in the copy buffer;

wherein the request to write the data to the different storage location is a request to copy the data from the entry in the copy buffer to the different storage location.

8. The method of claim 7, further comprising:

before the request to write the data to the different storage location is received;

receiving a request to write the storage location from a host processor; and

performing the write to the entry of the copy buffer.

9. The method of claim 7, further comprising:

before the request to write the data to the different storage location is received;

receiving a request to read the storage location from a host processor;

reading the entry of the copy buffer to obtain the data; and

returning the data read from the copy buffer in response to the request to read the storage location.

10. The method of claim 9,

wherein the memory controller comprises an address translation table;

wherein the method further comprises;

in response to detecting the failure of the write of data to the storage location in the non-volatile memory, updating the address translation table to map the storage location to the entry of the copy buffer; and

after the request to read the data at the different storage location is received, accessing the address translation table to identify the entry of the copy buffer to read.

11. The method of claim 10, further comprising:

after the write of the data to the different storage location is successfully performed;

updating, by a microcontroller for the non-volatile memory, a memory mapped unit (MMU) to map the storage location to the different storage location; and

updating the address translation table to remove the mapping of the storage location to the entry of the copy buffer.

12. The method of claim 5, wherein detecting the failure of the write of data to the storage location in the non-volatile memory comprises reading an error mode for the storage location at the non-volatile memory.

13. The method of claim 5, wherein the write is received from a host processor that hosts a virtualization platform and wherein the write is performed on behalf of a virtual resource implemented based on the virtualization platform.

14. A memory controller for a non-volatile memory, the memory controller comprising circuitry configured to:

receive a request to write data to a storage location in the non-volatile memory from a host processor connected to the memory controller;

perform the write of the data to the storage location in the non-volatile memory;

detect a failure of the write of the data to the storage location in the non-volatile memory;

send an indication of the failed write to the storage location to a microcontroller for the non-volatile memory;

receive a request to write the data to a different storage location in the non-volatile memory from the microcontroller; and

perform the write of the data to the different storage location in the non-volatile memory.

15. The memory controller of claim 14, wherein the memory controller is further configured to:

in response to the detection of the failure of the write of data to the storage location in the non-volatile memory;

identify an entry in the copy buffer for the data; and

store the data in the entry in the copy buffer;

wherein the request to write the data to the different storage location is a request to copy the data from the entry in the copy buffer to the different storage location.

16. The memory controller of claim 15,

wherein the memory controller comprises an address translation table;

and

wherein the memory controller is further configured to;

in response to the detection of the failure of the write of data to the storage location in the non-volatile memory, update the address translation table to map the storage location to the entry of the copy buffer; and

before the request to write the data to the different storage location is received;

receive a request to read the storage location;

access the address translation table to identify the entry of the copy buffer to read;

read the entry of the copy buffer to obtain the data; and

return the data read from the copy buffer in response to the request to read the storage location.

17. The memory controller of claim 16,

wherein the circuitry of the memory controller is further configured to:

after the detection of a migration event for other data at another storage location in the non-volatile memory at the microcontroller;

identify another entry in the copy buffer;

write the other data to the other entry in the copy buffer;

update the address translation table to map the other storage location to the other entry of the copy buffer; and

before the other data is written to a destination location in the non-volatile memory for the migration event;

receive a request to read the other storage location;

access the address translation table to identify the other entry in the copy buffer to read;

read the other entry of the copy buffer to obtain the other data; and

return the other data read from the copy buffer in response to the request to read the other storage location.

18. The memory controller of claim 16, wherein the circuitry of the memory controller is further configured to:

after the detection of a migration event for other data at another storage location in the non-volatile memory at the microcontroller;

identify another entry in the copy buffer;

write the other data to the other entry in the copy buffer;

update the address translation table to map the other storage location to the other entry of the copy buffer; and

after the other data is written to a destination location for the migration event, update the address translation table to map the other storage location to the destination location for the migration event;

after the update to the address translation table to map the other storage location to the destination location;

receive a request to read the other storage location;

access the address translation table to identify the destination location in the non-volatile memory to read;

read the destination location in the non-volatile memory to obtain the other data; and

return the other data read from the non-volatile memory in response to the request to read the other storage location.

19. The memory controller of claim 15, wherein the circuitry of the memory controller is further configured to:

detect a failure of the write of the data to the different storage location in the non-volatile memory; and

in response to the detection of the failure of the write of data to the storage location, update a status for the entry in the copy buffer to indicate a migration failure.

20. The memory controller of claim 14, wherein the memory controller is implemented as part of an access device for the non-volatile memory, and wherein the access device is an application specific integrated circuit (ASIC), a system-on-chip (SoC), or a field-programmable gate array (FPGA).