Random number generator

• US 10,459,692 B2
• Filed: 09/13/2016
• Issued: 10/29/2019
• Est. Priority Date: 03/16/2016
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takaya, Satoshi, Yasuda, Shinichi, Tanamoto, Tetsufumi, Fujita, Shinobu
• Primary Examiner(s): Rashid, Harunur
• Application Number:
  US15/263,972
• Publication Number:
  US 20170269904A1
• Time in Patent Office: 1,141 Days
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H04L 2209/08 Randomization, e.g. dummy operations or using noise
• CPC Class Codes: H04L 9/0869 involving random numbers or seeds

Abstract

According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.

Claims

1. A random number generator comprising:

a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal;

a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal;

a third circuit which outputs a control signal on the basis of the values; and

a fourth circuit which controls the first circuit on the basis of the control signal so as to increase the predetermined duty ratio when the predetermined duty ratio is less than 50% and to decrease the predetermined duty ratio when the predetermined duty ratio is greater than 50%,

wherein the first circuit includes a first sub-circuit functioning as an inverter circuit and a second sub-circuit functioning as an inverter circuit,

the first sub-circuit includes a first P-channel FET circuit portion including at least one P-channel FET and a first N-channel FET circuit portion including at least one N-channel FET and connected in series to the first P-channel FET circuit portion, a driving force of the first P-channel FET circuit portion being greater than that of the first N-channel FET circuit portion,

the second sub-circuit includes a second P-channel FET circuit portion including at least one P-channel FET and a second N-channel FET circuit portion including at least one N-channel FET and connected in series to the second P-channel FET circuit portion, a driving force of the second N-channel FET circuit portion being greater than that of the second P-channel FET circuit portion, and

the predetermined duty ratio is increased by selecting one of the first and second sub-circuits, and the predetermined duty ratio is decreased by selecting the other one of the first and second sub-circuits.

2. The random number generator of claim 1, further comprising a fifth circuit which generates the first oscillation signal.

3. The random number generator of claim 2, wherein the fifth circuit comprises a ring oscillator.

4. The random number generator of claim 1, wherein

the second circuit comprises latch portions connected in series, and

the values are latched in the latch portions, respectively.

5. The random number generator of claim 1, wherein the second circuit latches the values on the basis of a rising edge or a falling edge of the clock.

6. The random number generator of claim 5, wherein the second circuit comprises a flip-flop circuit.

7. The random number generator of claim 1, wherein each of the values includes 0 or 1.

8. The random number generator of claim 7, wherein the third circuit outputs the control signal showing a relationship between a number of 0s and a number of 1s on the basis of the values.

9. The random number generator of claim 8, wherein the third circuit outputs the control signal showing that the number of 0s is larger than the number of 1s, and the predetermined duty ratio is larger than a duty ratio of the first oscillation signal.

10. The random number generator of claim 8, wherein the third circuit outputs the control signal showing that the number of 1s is larger than the number of 0s, and the predetermined duty ratio is smaller than a duty ratio of the first oscillation signal.

11. The random number generator of claim 1, wherein the frequency of the second oscillation signal has a value between 100 mega Hz and 2 giga Hz, and the frequency of the clock has a value between 1 mega Hz and 50 mega Hz.

12. The random number generator of claim 1, wherein the first circuit further includes a third sub-circuit functioning as an inverter circuit, and

the third sub-circuit includes a third P-channel FET circuit portion including at least one P-channel FET and a third N-channel FET circuit portion including at least one N-channel FET and connected in series to the third P-channel FET circuit portion, a driving force of the third P-channel FET circuit portion being equal to that of the third N-channel FET circuit portion.

13. The random number generator of claim 12, wherein the first sub-circuit includes a NAND-gate circuit which includes the first P-channel FET circuit portion and the first N-channel FET circuit portion, and the second sub-circuit includes a NOR-gate circuit which includes the second P-channel FET circuit portion and the second N-channel FET circuit portion.

14. The random number generator of claim 12, wherein the first sub-circuit includes a first inverter circuit which includes a first P-channel FET and a first N-channel FET, a driving force of the first P-channel FET being greater than that of the first N-channel FET, and

the second sub-circuit includes a second inverter circuit which includes a second P-channel FET and a second N-channel FET, a driving force of the second N-channel FET being greater than that of the second P-channel FET.

15. A random number generating device comprising:

random number generators each comprising;

a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal;

a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal;

a third circuit which outputs a control signal on the basis of the values;

a fourth circuit which controls the first circuit on the basis of the control signal so as to increase the predetermined duty ratio when the predetermined duty ratio is less than 50% and to decrease the predetermined duty ratio when the predetermined duty ratio is greater than 50%; and

a post-processing unit which performs logical processing of output signals from the random number generators and outputs a random number,

wherein the first circuit includes a first sub-circuit functioning as an inverter circuit and a second sub-circuit functioning as an inverter circuit,

the first sub-circuit includes a first P-channel FET circuit portion including at least one P-channel FET and a first N-channel FET circuit portion including at least one N-channel FET and connected in series to the first P-channel FET circuit portion, a driving force of the first P-channel FET circuit portion being greater than that of the first N-channel FET circuit portion,

the second sub-circuit includes a second P-channel FET circuit portion including at least one P-channel FET and a second N-channel FET circuit portion including at least one N-channel FET and connected in series to the second P-channel FET circuit portion, a driving force of the second N-channel FET circuit portion being greater than that of the second P-channel FET circuit portion, and

the predetermined duty ratio is increased by selecting one of the first and second sub-circuits, and the predetermined duty ratio is decreased by selecting the other one of the first and second sub-circuits.

16. A system comprising:

a random number generating comprising;

random number generators each comprising;

a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal;

a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal;

a third circuit which outputs a control signal on the basis of the values; and

a fourth circuit which controls the first circuit on the basis of the control signal so as to increase the predetermined duty ratio when the predetermined duty ratio is less than 50% and to decrease the predetermined duty ratio when the predetermined duty ratio is greater than 50%;

a post-processing unit which performs logical processing of output signals from the random number generators and outputs a random number;

a security module which generates an encryption key using the random number from the random number generating device and encrypts/decrypts data; and

a communication module which transmits/receives the data,

wherein the first circuit includes a first sub-circuit functioning as an inverter circuit and a second sub-circuit functioning as an inverter circuit,

the first sub-circuit includes a first P-channel FET circuit portion including at least one P-channel FET and a first N-channel FET circuit portion including at least one N-channel FET and connected in series to the first P-channel FET circuit portion, a driving force of the first P-channel FET circuit portion being greater than that of the first N-channel FET circuit portion,

the second sub-circuit includes a second P-channel FET circuit portion including at least one P-channel FET and a second N-channel FET circuit portion including at least one N-channel FET and connected in series to the second P-channel FET circuit portion, a driving force of the second N-channel FET circuit portion being greater than that of the second P-channel FET circuit portion, and

the predetermined duty ratio is increased by selecting one of the first and second sub-circuits, and the predetermined duty ratio is decreased by selecting the other one of the first and second sub-circuits.