Random code generator with differential cells and associated control method

• US 10,459,693 B2
• Filed: 07/27/2018
• Issued: 10/29/2019
• Est. Priority Date: 10/13/2017
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lin, Chun-Hung, Lu, Chun-Hung, Huang, Shih-Chan
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/047,343
• Publication Number:
  US 20190114144A1
• Time in Patent Office: 459 Days
• Field of Search: 36518518
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Claims

1. A random code generator, comprising:

a power circuit for providing a supply voltage to a node;

a differential cell array comprising plural differential cells, wherein each differential cell comprises two sub-cells, a first terminal of the differential cell array is connected with the node through a control line, a second terminal of the differential cell array is connected with a word line, a third terminal of the differential cell array is connected with a first bit line, and a fourth terminal of the differential cell array is connected with a second bit line;

a voltage detector connected with the node for detecting a node voltage of the node;

a read/write circuit connected with the first bit line and the second bit line; and

a control circuit connected with the word line, the power circuit, the voltage detector and the read/write circuit,

wherein during enrollment, the power circuit provides the supply voltage to the control line, the read/write circuit provides a ground voltage to the first bit line and the second bit line, and the control circuit provides a select voltage to the word line to enroll a selected differential cell of the differential cell array, so that one of the two sub-cells is programmed to an on state, and the other of the two sub-cells is subjected to a program inhibition and in an off state,

wherein the read/write circuit judges a storage state of the selected differential cell and determines a bit of a random code according to the storage state of the selected differential cell.

2. The random code generator as claimed in claim 1, wherein the power circuit comprises:

a voltage source for outputting the supply voltage; and

a charging circuit comprising a switch and a capacitor, wherein a first terminal of the switch receives the supply voltage, a second terminal of the switch is connected with the node, the capacitor is connected with the node, and the node is connected with the control line,

during the enrollment, the switch is closed for a short time period and then opened, so that the supply voltage is charged to the capacitor and provided to the control line.

3. The random code generator as claimed in claim 2, wherein if a descending slope of the node voltage is not higher than a predetermined descending slope, the switch is closed for a short time period again and then opened, so that the supply voltage is charged to the capacitor again.

4. The random code generator as claimed in claim 1, wherein the power circuit is a limited-current circuit, wherein a current to be transmitted to the node is clamped to a preset current range by the limited-current circuit.

5. The random code generator as claimed in claim 1, wherein the selected differential cell comprises:

a first sub-cell comprising at least one first select transistor and at least one first floating gate transistor, wherein a source terminal of the at least one first select transistor is connected with the first terminal of the differential cell array, a gate terminal of the at least one first select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one first select transistor is connected with a source terminal of the at least one first floating gate transistor, a drain terminal of the at least one first floating gate transistor is connected with the third terminal of the differential cell array, and a gate terminal of the at least one first floating gate transistor is in a floating state; and

a second sub-cell comprising at least one second select transistor and at least one second floating gate transistor, wherein a source terminal of the at least one second select transistor is connected with the first terminal of the differential cell array, a gate terminal of the at least one second select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one second select transistor is connected with a source terminal of the at least one second floating gate transistor, a drain terminal of the at least one second floating gate transistor is connected with the fourth terminal of the differential cell array, and a gate terminal of the at least one second floating gate transistor is in the floating state,

wherein the numbers of the at least one first select transistor and the at least one first floating gate transistor in the first sub-cell and the numbers of the at least one second select transistor and the at least one second floating gate transistor in the second sub-cell are equal.

6. The random code generator as claimed in claim 1, wherein the selected differential cell comprises:

a first sub-cell comprising at least one first select transistor and at least one first antifuse transistor, wherein a source terminal of the at least one first select transistor is connected with the third terminal of the differential cell array, a gate terminal of the at least one first select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one first select transistor is connected with a source terminal of the at least one first antifuse transistor, a gate terminal of the at least one first antifuse transistor is connected with the first terminal of the differential cell array, and a drain terminal of the at least one first antifuse transistor is in a floating state; and

a second sub-cell comprising at least one second select transistor and at least one second antifuse transistor, wherein a source terminal of the at least one second select transistor is connected with the fourth terminal of the differential cell array, a gate terminal of the at least one second select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one second select transistor is connected with a source terminal of the at least one second antifuse transistor, a gate terminal of the at least one second antifuse transistor is connected with the first terminal of the differential cell array, and a drain terminal of the at least one second antifuse transistor is in the floating state,

wherein the numbers of the at least one first select transistor and the at least one first antifuse transistor in the first sub-cell and the numbers of the at least one second select transistor and the at least one second antifuse transistor in the second sub-cell are equal.

7. The random code generator as claimed in claim 1, wherein if the node voltage is lower than a predetermined voltage, the control circuit controls the read/write circuit to judge the storage state of the selected differential cell.

8. The random code generator as claimed in claim 1, wherein the random code generator further comprises a write buffer, and the write buffer is connected with the control circuit, the read/write circuit, the first bit line and the second bit line, wherein after the read/write circuit judges the storage state of the selected differential cell, the write buffer programs the selected differential cell to the storage state again.

9. The random code generator as claimed in claim 8, wherein while the write buffer programs the selected differential cell to the storage state again, the power circuit provides the supply voltage to the control line stably.

10. A control method for a random code generator, the random code generator comprising a differential cell array, a capacitor, a voltage detector, a read/write circuit and a control circuit, the differential cell array comprising plural differential cells, each differential cell comprising two sub-cells, a first terminal of the differential cell array being connected with a control line, a second terminal of the differential cell array being connected with a word line, a third terminal of the differential cell array being connected with a first bit line, a fourth terminal of the differential cell array being connected with a second bit line, the capacitor being connected with a node, the node being connected with the control line, the voltage detector being connected with the node for detecting a node voltage of the node, the read/write circuit being connected with the first bit line and the second bit line, the control circuit being connected with the word line, the voltage detector and the read/write circuit, the control method comprising steps of:

(a) charging the capacitor to a supply voltage;

(b) enrolling a selected differential cell of the differential cell array according to the supply voltage of the capacitor; and

(c) if the node voltage of the node is lower than a predetermined voltage, the read/write circuit judges a storage state of the selected differential cell and determines a bit of a random code according to the storage state of the selected differential cell.

11. The control method as claimed in claim 10, wherein before the step (c), the control method further comprises steps:

if a descending slope of the node voltage is not higher than a predetermined descending slope, performing the step (a) again; and

if the descending slope of the node voltage is higher than the predetermined descending slope, performing the step (c).

12. The control method as claimed in claim 10, wherein in the step (b), the supply voltage is provide from the capacitor to the control line, a ground voltage is provided to the first bit line and the second bit line, a select voltage is provided to the word line, so that one of the two sub-cells is programmed to an on state, and the other of the two sub-cells is subjected to a program inhibition and in an off state.

13. The control method as claimed in claim 10, wherein the random code generator further comprises a write buffer, and the write buffer is connected with the control circuit, the read/write circuit, the first bit line and the second bit line, wherein after the read/write circuit judges the storage state of the selected differential cell, the write buffer programs the selected differential cell to the storage state again.

14. The control method as claimed in claim 13, wherein while the write buffer programs the selected differential cell to the storage state again, the supply voltage is provided to the control line stably.

15. The control method as claimed in claim 10, wherein the selected differential cell comprises:

a first sub-cell comprising at least one first select transistor and at least one first floating gate transistor, wherein a source terminal of the at least one first select transistor is connected with the first terminal of the differential cell array, a gate terminal of the at least one first select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one first select transistor is connected with a source terminal of the at least one first floating gate transistor, a drain terminal of the at least one first floating gate transistor is connected with the third terminal of the differential cell array, and a gate terminal of the at least one first floating gate transistor is in a floating state; and

a second sub-cell comprising at least one second select transistor and at least one second floating gate transistor, wherein a source terminal of the at least one second select transistor is connected with the first terminal of the differential cell array, a gate terminal of the at least one second select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one second select transistor is connected with a source terminal of the at least one second floating gate transistor, a drain terminal of the at least one second floating gate transistor is connected with the fourth terminal of the differential cell array, and a gate terminal of the at least one second floating gate transistor is in the floating state,

wherein the numbers of the at least one first select transistor and the at least one first floating gate transistor in the first sub-cell and the numbers of the at least one second select transistor and the at least one second floating gate transistor in the second sub-cell are equal.

16. The control method as claimed in claim 10, wherein the selected differential cell comprises:

a first sub-cell comprising at least one first select transistor and at least one first antifuse transistor, wherein a source terminal of the at least one first select transistor is connected with the third terminal of the differential cell array, a gate terminal of the at least one first select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one first select transistor is connected with a source terminal of the at least one first antifuse transistor, a gate terminal of the at least one first antifuse transistor is connected with the first terminal of the differential cell array, and a drain terminal of the at least one first antifuse transistor is in a floating state; and

a second sub-cell comprising at least one second select transistor and at least one second antifuse transistor, wherein a source terminal of the at least one second select transistor is connected with the fourth terminal of the differential cell array, a gate terminal of the at least one second select transistor is connected with the second terminal of the differential cell array, a drain terminal of the at least one second select transistor is connected with a source terminal of the at least one second antifuse transistor, a gate terminal of the at least one second antifuse transistor is connected with the first terminal of the differential cell array, and a drain terminal of the at least one second antifuse transistor is in the floating state,

wherein the numbers of the at least one first select transistor and the at least one first antifuse transistor in the first sub-cell and the numbers of the at least one second select transistor and the at least one second antifuse transistor in the second sub-cell are equal.