Instruction-set simulator and its simulator generation method

• US 10,459,707 B2
• Filed: 01/23/2018
• Issued: 10/29/2019
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Original Assignee: Tokyo Institute of Technology (National University Corporation Tokyo Institute of Technology)
• Inventors: Isshiki, Tsuyoshi
• Primary Examiner(s): Zhen, Wei Y
• Assistant Examiner(s): Bourzik, Brahim
• Application Number:
  US15/877,397
• Publication Number:
  US 20180165079A1
• Time in Patent Office: 644 Days
• Field of Search: 717136
• CPC Class Codes: G06F 8/31 Programming languages or programming paradigms
• CPC Class Codes: G06F 8/53 Decompilation; Disassembly

Abstract

Providing an instruction-set simulator and a method for generating such simulator that is capable or guaranteeing the full restoration of source program file from the binary executable program, in which the generated source program is easy to analyze, and the simulation speed is considerably fast.

Claims

1. An instruction-set simulator which generates a simulator executable program by converting a binary executable program into a source program, comprising:

a subroutine detection means that detects subroutines included in the binary executable program,

a branch instruction detection means that detects the branch instructions in the binary executable program which have a branch target address,

a subroutine-call instruction detection means that detects subroutine-call instructions in the binary executable program which have a subroutine-call target address,

a subroutine source program output means that generates the source program for each subroutine detected by the subroutine detection means,

a label annotation means that annotates a label indicating the branch target address at a branch target instruction in the generated source program,

an unconditional branch instruction output means that converts each branch instruction in the binary executable program into an unconditional branch instruction in the generated source program which branches to the labeled branch target instruction in the generated source program, and

a subroutine-call instruction output means that converts each subroutine-call instruction in the binary executable program into a subroutine-call instruction in the generated source program.

2. The instruction-set simulator according to claim 1, wherein the branch instruction detection means comprises

a simple branch instruction detection means that detects simple branch instructions whose branch target address can be statically determined, and

a data-dependent branch instruction detection means that detects data-dependent branch instructions whose branch target address is determined by a register value or a memory value.

3. The instruction-set simulator according to claim 2, wherein the instruction-set simulator comprises

a jump-table recording means that records the branch target addresses of the data-dependent branch instructions into a jump-table information storage unit, and

a data-dependent branch instruction generation means that generates a set of unconditional branch instructions from a jump-table information in the generated source program, in which the jump-table information is retrieved from the jump-table information storage unit by searching the branch target address of the data-dependent branch instruction registered in the jump-table information storage unit.

4. The instruction-set simulator according to claim 1, wherein the subroutine-call instruction detection means comprises

a simple subroutine-call instruction detection means that detects simple subroutine-call instructions whose call target address can be statically identified, and

a data-dependent subroutine-call instruction detection means that detects data-dependent subroutine-call instructions whose call target address is determined by a register value or a memory value.

5. The instruction-set simulator according to claim 4, wherein the subroutine-call instruction output means comprises

a machine instruction subroutine address table generation means that generates a machine instruction subroutine address table whose table entry is composed of a subroutine name and a subroutine address in the binary executable program,

a subroutine address search program generation means that generates a program which searches for the subroutine address in the generated source program from the subroutine address in the binary executable program, and

a data-dependent subroutine-call instruction generation means that generates data-dependent subroutine-call instructions in the generated source program in which the target call address of the data-dependent subroutine-call instruction is resolved by the subroutine address search program.

6. The instruction-set simulator according to claim 1, wherein the instruction-set simulator comprises

a register variable conversion means that converts the register values in the binary executable program into subroutine'"'"'s argument variables or subroutine'"'"'s local variables of the generated source program.

7. The instruction-set simulator according to claim 1, wherein

the generated source program is a C program,

unconditional branch instructions to the labeled instructions and subroutine-call instructions are used instead of relying on a program structure that comprises switch-statements on the program counter and case-statements corresponding to individual instructions in the binary executable program,

each of the subroutines in the binary executable program correspond to the subroutines in the generated source program, and

a hierarchical structure of subroutines in the binary executable program is restored as a hierarchical structure of subroutines in the generated source program.

8. The instruction-set simulator according to claim 1, wherein the instruction-set simulator comprises

an unregistered machine instruction address detection means that detects and records an unresolved target call address of a data-dependent subroutine-call instruction then forcibly terminates the instruction-set simulator, a case which can be caused by the absence of symbol information in the binary executable program that can cause some of the subroutines in the binary executable program to remain undetected, and

an unregistered subroutine source program output means that emits the source program for the unregistered subroutine.

9. A method for generating a simulator executable program by an instruction-set simulator for converting a binary executable program into a source program to generate the simulator executable program,

wherein the instruction-set simulator comprises a subroutine detection means, a branch instruction detection means, a subroutine-call instruction detection means, a subroutine source program output means, a label annotation means, an unconditional branch instruction output means, and a subroutine-call instruction source program output means,

the method comprising steps of:

detecting, by the subroutine detection means, subroutines included in the binary executable program,

detecting, by the branch instruction detection means, the branch instructions in the binary executable program which have a branch target address,

detecting, by the subroutine-call instruction detection means, subroutine-call instructions in the binary executable program which have a subroutine-call target address,

generating, by the subroutine source program output means, the source program for each subroutine detected by the subroutine detection means,

annotating, by the label annotation means, a label indicating the branch target address at a branch target instruction in the generated source program,

converting, by the unconditional branch instruction output means, each branch instruction in the binary executable program into an unconditional branch instruction in the generated source program which branches to the labeled branch target instruction in the generated source program, and

converting, by the subroutine-call instruction source program output means, each subroutine-call instruction in the binary executable program into a subroutine-call instruction in the generated source program.

10. The method for generating the simulator executable program according to claim 9, wherein the instruction-set simulator comprises a jump-table recording means and a data-dependent branch instruction generation means,

wherein the method comprises steps of:

recording, by the jump-table recording means, the branch target addresses of the data-dependent branch instructions into a jump-table information storage unit, and

generating, by the data-dependent branch instruction generation means, a set of unconditional branch instructions from the jump-table information in the generated source program, in which the jump-table information is retrieved from the jump-table information storage unit by searching the branch target address of the data-dependent branch instruction registered in the jump-table information storage unit.

11. The method for generating the simulator executable program according to claim 9,

wherein the instruction-set simulator comprises a machine instruction subroutine address table generation means, a subroutine address search program generation means and a data-dependent subroutine-call instruction generation means,

wherein the method comprises steps of:

generating, by the machine instruction subroutine address table generation means, a machine instruction subroutine address table whose table entry is composed of a subroutine name and a subroutine address in the binary executable program,

generating, by the subroutine address search program generation means, a program which searches for the subroutine address in the generated source program from the subroutine address in the binary executable program, and

generating, by the data-dependent subroutine-call instruction generation means, data-dependent subroutine-call instructions in the generated source program in which the target call address of the data-dependent subroutine-call instruction is resolved by the subroutine address search program.

12. The method for generating the simulator executable program according to claim 9,

wherein the instruction-set simulator comprises a register variable conversion means,

wherein the method comprises a step of:

converting, by the register variable conversion means, the register values in the binary executable program into subroutine'"'"'s argument variables or subroutine'"'"'s local variables of the generated source program.

13. The method for generating the simulator executable program according to claim 9,

wherein the instruction-set simulator comprises an unregistered machine instruction address detection means and an unregistered subroutine source program output means,

wherein the method comprises steps of:

detecting and recording, by the unregistered machine instruction address detection means, an unresolved target call address of a data-dependent subroutine-call instruction, and then forcibly terminating the instruction-set simulator, a case which can be caused by the absence of symbol information in the binary executable program that can cause some of the subroutines in the binary executable program to remain undetected, and

emitting, by the unregistered subroutine source program output means, the source program for the unregistered subroutine.