Memory device, and data processing method based on multi-layer RRAM crossbar array

• US 10,459,724 B2
• Filed: 07/17/2018
• Issued: 10/29/2019
• Est. Priority Date: 01/18/2016
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.), Nanyang Technological University
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Yu, Hao, Wang, Yuhao, Zhao, Junfeng, Yang, Wei, Xiao, Shihai, Ni, Leibin
• Primary Examiner(s): Mai, Tan V
• Application Number:
  US16/037,767
• Publication Number:
  US 20180321942A1
• Time in Patent Office: 469 Days
• Field of Search: 708835
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 7/00 Methods or arrangements for processing data by operating upon the order or content of the data handled logic circuits H03K19/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06J 1/00 Hybrid computing arrangements digitally-programmed analogue computers G06G7/06
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Embodiments of the present disclosure provide a memory device. The memory device includes an RRAM crossbar array that is configured to perform a logic operation, and resistance values of resistors in the RRAM crossbar array are all set to R_on or R_off to indicate a value 1 or 0. Based on the foregoing setting, an operation is implemented using the RRAM crossbar array, so that reliability of a logic operation of the RRAM crossbar array can be improved.

Claims

1. A data processing apparatus comprising:

a control bus; and

multiple memory units connected by the control bus, each of the multiple memory units comprising a control circuit and a computation circuit,

wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar array and a format conversion circuit, the first RRAM crossbar array having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds, and outputs of the comparator circuits are connected to the format conversion circuit;

wherein the control circuit is connected to the control bus and configured to;

receive a computation instruction for performing a vector multiplication of vector A and vector B;

setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B;

setting the word lines of the first RRAM crossbar array according to elements of vector A;

wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B;

the format conversion circuit being set up to convert the outputs of the comparator circuits into an output corresponding to a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

2. The data processing apparatus according to claim 1, wherein the format conversion circuit comprises:

a second RRAM crossbar array connected to receive the outputs of the comparator circuits and configured to generate an output that corresponds to an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and

a third RRAM crossbar array connected to receive the output of the second RRAM crossbar array and configured to generate the output corresponding to the second binary number.

3. The data processing apparatus according to claim 2, wherein

the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows×

N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits;

the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j^th word line in the N word lines is a voltage value corresponding to B_j, a resistance value of a resistor in the j^th row at the first RRAM crossbar array is a resistance value corresponding to A_A, B_j is the j^th element of vector B, A_J is the j^th element of vector A, and a value of j ranges from 0 to N−

1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2;

the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B; and

the format conversion circuit receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and generates, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the format conversion circuit, voltage signals corresponding to the second binary number, wherein the second binary number is a binary representation of K.

4. The data processing apparatus according to claim 3, wherein the j^th comparator circuit in the N comparator circuits comprises a resistor R_s of a constant resistance value and a comparator, one end of the resistor R_s is connected to the j^th bit line in the N bit lines and the comparator, the other end of the resistor R_s is grounded, a voltage threshold of the j^th comparator circuit is V_r*g_on*R_s*(2j+1)/2, V_r indicates a voltage value corresponding to a value 1, and g_on indicates a reciprocal of R_on.

5. The data processing apparatus according to claim 4, wherein

the second RRAM crossbar array comprises a (2N−

1) rows×

N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array;

the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−

1 word lines, and performs a logic operation according to the voltage signal corresponding to the first computing result and a resistance value of a resistor at the second layer of RRAM crossbar array;

6. The data processing apparatus according to claim 5, wherein the j^th word line of the third RRAM crossbar array is connected to the j^th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j^th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.

7. The data processing apparatus according to claim 1, wherein vector A is a row vector of a matrix Φ

, vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix Φ and

a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix Φ and

the matrix X.

8. The data processing apparatus according to claim 1, wherein the instruction of the processor further comprises a data access instruction, and each memory unit further comprises:

a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.

9. A data processing apparatus comprising:

a control bus; and

a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit,

wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds;

wherein the control circuit is connected to the control bus and configured to;

receive a computation instruction for performing a vector multiplication of vector A and vector B;

setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B; and

setting the word lines of the first RRAM crossbar array according to elements of vector A;

wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.

10. The data processing apparatus according to claim 9, wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein

the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B;

and

the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

11. The data processing apparatus according to claim 10, wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows×

N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits;

the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j^th word line in the N word lines is a voltage value corresponding to 4, a resistance value of a resistor in the j^th row at the first RRAM crossbar array is a resistance value corresponding to A, 4 is the j^th element of vector B, A_j is the j^th element of vector A, and a value of j ranges from 0 to N−

1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2;

the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B;

the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits, and obtain, according to the voltage signals corresponding to the first binary number and resistance values of resistors in the second RRAM crossbar array, voltage signals corresponding to the intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B; and

the third RRAM crossbar array receives the voltage signals corresponding to the intermediate binary number from the bit lines of second RRAM crossbar array, and convert the intermediate binary number into the second binary number, wherein the second binary number is a binary representation of K.

12. The data processing apparatus according to claim 11, wherein the j^th comparator circuit in the N comparator circuits comprises a resistor R of a constant resistance value and a comparator, one end of the resistor R_s is connected to the j^th bit line in the N bit lines and the comparator, the other end of the resistor R_s is grounded, a voltage threshold of the j^th comparator circuit is V_r*g_on*R_s*(2j+1)/2, V_r indicates a voltage value corresponding to a value 1, and g_on indicates a reciprocal of R_on.

13. The data processing apparatus according to claim 11, wherein the second RRAM crossbar array comprises a (2N−

1) rows×

N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array;

the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−

1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array;

14. The data processing apparatus according to claim 13, wherein the j^th word line of the third RRAM crossbar array is connected to the j^th bit line of the second RRAM crossbar array, and a resistance value of a resistor in the j^th row of the third RRAM crossbar array corresponds to a binary representation of the integer j+1.

15. The data processing apparatus according to claim 9, wherein the memory device comprises multiple memory units, each of the multiple memory units comprises a control circuit and a computation circuit, vector A is a row vector of a matrix Φ

and vector B is a column vector of a matrix X, each of the multiple computation circuits in the memory device is set for performing point multiplication operations of a plurality of row vectors of the matrix Φ and

a plurality of column vectors of the matrix X, and the multiple computation circuits jointly implement a matrix multiplication operation of the matrix Φ and

the matrix X.

16. The data processing apparatus according to claim 9, wherein the instruction of the processor further comprises a data access instruction, and the memory unit further comprises:

a storage circuit, wherein the storage circuit is connected to the control circuit, and the control circuit read data from the computation circuit or write data into the computation circuit according to the data access instruction.

17. A computing device, comprising:

a processor configured to send a computation instruction;

a memory device connected to the processor, wherein the memory device comprising a control bus and a memory unit connected to the control bus, the memory unit comprising a control circuit and a computation circuit;

wherein the computation circuit comprises a first resistive random access memory (RRAM) crossbar having multiple rows and multiple columns of memory cells, multiple word lines connected to respective rows of memory cells, and a plurality of comparator circuits each connected to a corresponding column of the first RRAM crossbar array, wherein the comparator circuits are set to have incremental thresholds;

wherein the control circuit is connected to the control bus and configured to;

receive the computation instruction for performing a vector multiplication of vector A and vector B;

setting the memory cells in the first RRAM crossbar array such that states of memory cells of each column of the first RRAM crossbar array correspond to elements of vector B;

setting the word lines of the first RRAM crossbar array according to elements of vector A;

wherein the outputs of the comparator circuits are voltage signals corresponding to a first binary number in which a number of bits with a value 1 indicates a numerical result of multiplication of vector A and vector B.

18. The computing device according to claim 17, wherein the computation circuit further comprises a second RRAM crossbar array and a third RRAM crossbar array each having multiple rows and multiple columns of memory cells and multiple word lines connected to respective rows of memory cells, wherein outputs of the comparator circuits are connected to corresponding word lines of the second RRAM crossbar array, outputs of the second RRAM crossbar array are connected to corresponding words lines of the third RRAM crossbar array, wherein

the second RRAM crossbar array being set up to convert the outputs of the comparator circuits into an output representing an intermediate binary number in which a location of a bit with a value 1 indicates the numerical result of multiplication of vector A and vector B;

and

the third RRAM crossbar array being set up to convert the output of the second RRAM crossbar array into an output representing a second binary number having a numerical value equal to the numerical result of multiplication of vector A and vector B.

19. The computing device according to claim 18, wherein the multiple rows and multiple columns of memory cells in the first RRAM crossbar array comprise N rows x N columns resistors, an input end of a resistor in each row at the first RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the first RRAM crossbar array is connected to a bit line, N word lines of the first RRAM crossbar array are connected to the control circuit, and each of N bit lines of the first RRAM crossbar array are respectively connected to a comparator circuit of the plurality of comparator circuits;

the first RRAM crossbar array generates N current signals on the N bit lines according to voltage signals input by the N word lines and a resistance value of a resistor at the first RRAM crossbar array, a voltage value of a voltage signal input by the j^th word line in the N word lines is a voltage value corresponding to B_j, a resistance value of a resistor in the j^th row at the first RRAM crossbar array is a resistance value corresponding to A_j, B_j is the j^th element of vector B, A_j is the j^th element of vector A, and a value of j ranges from 0 to N−

1, wherein each of vector A and vector B indicates an N-dimensional vector, each elements of vector A and vector B indicates a value 1 or 0, and N is a positive integer not less than 2;

the N comparator circuits respectively convert the N current signals into N voltage signals, and compare the N voltage signals with voltage thresholds respectively corresponding to the N comparator circuits, to output, from output ends of the N comparator circuits, the voltage signals corresponding to the first binary number, wherein the first binary number is an N-dimensional vector, first K elements of the first binary number are 1, remaining elements are 0, and K is the result of multiplication of vector A and vector B;

the second RRAM crossbar array comprises a (2N−

1) rows×

N columns resistor array, an input end of a resistor in each row at the second RRAM crossbar array is connected to a word line, an output end of a resistor in each column at the second RRAM crossbar array is connected to a bit line, and each of word lines of the second RRAM crossbar array is connected to a output end of a comparator circuit in the first RRAM crossbar array;

the second RRAM crossbar array receives the voltage signals corresponding to the first binary number from the output ends of the comparator circuits of the first RRAM crossbar array through the 2N−

1 word lines, and performs a logic operation according to the voltage signals corresponding to the first binary number and a resistance value of a resistor at the second RRAM crossbar array;

20. The computing device according to claim 19, wherein the j^th comparator circuit in the N comparator circuits comprises a resistor R_s of a constant resistance value and a comparator, one end of the resistor R_s is connected to the j^th bit line in the N bit lines and the comparator, the other end of the resistor R_s is grounded, a voltage threshold of the j^th comparator circuit is V_r*g_on*R_s*(2j+1)/2, V_r indicates a voltage value corresponding to a value 1, and g_on indicates a reciprocal of R_on.