Apparatus and method of improved insert instructions

• US 10,459,728 B2
• Filed: 11/10/2017
• Issued: 10/29/2019
• Est. Priority Date: 12/23/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ould-Ahmed-Vall, Elmoustapha, Valentine, Robert, Corbal, Jesus, Toll, Bret L., Charney, Mark J., Sperber, Zeev, Gradstein, Amit
• Primary Examiner(s): Geib, Benjamin P
• Assistant Examiner(s): Nguyen, William V
• Application Number:
  US15/809,721
• Publication Number:
  US 20180074825A1
• Time in Patent Office: 718 Days
• CPC Class Codes: G06F 12/0615 Address space extension
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30038 using a mask
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3802 Instruction prefetching

Abstract

An apparatus is described having instruction execution logic circuitry to execute first, second, third and fourth instruction. Both the first instruction and the second instruction insert a first group of input vector elements to one of multiple first non overlapping sections of respective first and second resultant vectors. The first group has a first bit width. Each of the multiple first non overlapping sections have a same bit width as the first group. Both the third instruction and the fourth instruction insert a second group of input vector elements to one of multiple second non overlapping sections of respective third and fourth resultant vectors. The second group has a second bit width that is larger than said first bit width. Each of the multiple second non overlapping sections have a same bit width as the second group. The apparatus also includes masking layer circuitry to mask the first and third instructions at a first resultant vector granularity, and, mask the second and fourth instructions at a second resultant vector granularity.

Claims

1. A processor comprising:

a plurality of vector registers including a source vector register and a destination vector register;

instruction decode circuitry to decode an insert instruction, the insert instruction including a vector extension component and an immediate, the vector extension component comprising;

a first byte field to indicate a format of the insert instruction,

a second byte field to identify one or more subsets of the plurality of vector registers, the one or more subsets including the source vector register and the destination vector register, and to identify a corresponding opcode map for the insert instruction, and

a third byte field to indicate a packed data element length and to specify a portion of an opcode encoding corresponding to the insert instruction; and

an execution circuit to perform operations specified by the insert instruction, wherein following the instruction decode circuitry decoding the insert instruction, the execution circuit is to read 128 bits of data from the source vector register and insert the 128 bits of data into a specified position in the destination vector register,

wherein the specified position in which to insert the 128 bits of data is selected based on the immediate.

2. The processor of claim 1 wherein the first byte field, second byte field, and third byte field are arranged sequentially in the insert instruction.

3. The processor of claim 1 wherein the destination vector register is from a different register space than the source vector register.

4. The processor of claim 1 wherein the 128 bits of data are stored as a packed data element in the source vector register.

5. The processor of claim 4 wherein the packed data element includes one or more integer values.

6. The processor of claim 1 wherein the source vector register is an N-bit register and the destination vector register is an M-bit register, where N>

M.

7. The processor of claim 6 wherein the source vector register is a YMM register and the destination vector register is an XMM register.

8. The processor of claim 1 wherein the third byte field further comprises:

a four-bit field to indicate a specific source vector register or destination vector register for certain instructions other than the insert instruction, the four-bit field set to 1111 in the insert instruction to indicate that the four-bit field does not encode an operand.

9. The processor of claim 1 further comprising:

a scale, index, and base (SIB) byte usable to perform address generation for the insert instruction.

10. The processor of claim 1 further comprising:

a displacement factor byte including a displacement field usable for address generation.

11. A method comprising:

decoding an insert instruction by instruction decode circuitry, the decoding to cause a plurality of vector registers to be accessed including a source vector register and a destination vector register;

the insert instruction including a vector extension component and an immediate, the vector extension component comprising;

a first byte field to indicate a format of the insert instruction,

a second byte field to identify one or more subsets of the plurality of vector registers, the one or more subsets including a source vector register and a destination vector register, and to identify a corresponding opcode map for the insert instruction, and

a third byte field to indicate a packed data element length and to specify a portion of an opcode encoding corresponding to the insert instruction; and

performing operations specified by the insert instruction following the decoding of the insert instruction, the operations including reading 128 bits of data from the source vector register and inserting the 128 bits of data into a specified position in the destination vector register, wherein the specified position in which to insert the 128 bits of data is selected based on the immediate.

12. The method of claim 11 wherein the first byte field, second byte field, and third byte field are arranged sequentially in the insert instruction.

13. The method of claim 11 wherein the destination vector register is from a different register space than the source vector register.

14. The method of claim 11 wherein the 128 bits of data are stored as a packed data element in the source vector register.

15. The method of claim 14 wherein the packed data element includes one or more integer values.

16. The method of claim 11 wherein the source vector register is an N-bit register and the destination vector register is an M-bit register, where N>

M.

17. The method of claim 16 wherein the source vector register is a YMM register and the destination vector register is an XMM register.

18. The method of claim 11 wherein the third byte field further comprises:

a four-bit field to indicate a specific source register or destination vector register for certain instructions other than the insert instruction, the four-bit field set to 1111 in the insert instruction to indicate that the four-bit field does not encode an operand.

19. The method of claim 11 further comprising:

performing address generation for the insert instruction using a scale, index, and base (SIB) byte of the insert instruction.

20. The method of claim 11 further comprising:

performing address generation for the insert instruction using a displacement factor byte of the insert instruction.

21. A non-transitory machine-readable medium comprising program code which, when executed by a machine, causes the machine to perform operations of:

decoding an insert instruction by instruction decode circuitry, the decoding to cause a plurality of vector registers to be accessed including a source vector register and a destination vector register;

the insert instruction including a vector extension component and an immediate, the vector extension component comprising;

a first byte field to indicate a format of the insert instruction,

a second byte field to identify one or more subsets of the plurality of vector registers, the one or more subsets including a source vector register and a destination vector register, and to identify a corresponding opcode map for the insert instruction, and

a third byte field to indicate a packed data element length and to specify a portion of an opcode encoding corresponding to the insert instruction; and

performing operations specified by the insert instruction following the decoding of the insert instruction, the operations including reading 128 bits of data from the source vector register and inserting the 128 bits of data into a specified position in the destination vector register, wherein the specified position in which to insert the 128 bits of data is selected based on the immediate.

22. The non-transitory machine-readable medium of claim 21 wherein the first byte field, second byte field, and third byte field are arranged sequentially in the insert instruction.

23. The non-transitory machine-readable medium of claim 21 wherein the destination vector register is from a different register space than the source vector register.

24. The non-transitory machine-readable medium of claim 21 wherein the 128 bits of data are stored as a packed data element in the source vector register.

25. The non-transitory machine-readable medium of claim 24 wherein the packed data element includes one or more integer values.

26. The non-transitory machine-readable medium of claim 21 wherein the source vector register is an N-bit register and the destination vector register is an M-bit register, where N>

M.

27. The non-transitory machine-readable medium of claim 26 wherein the source vector register is a YMM register and the destination vector register is an XMM register.

28. The non-transitory machine-readable medium of claim 21 wherein the third byte field further comprises:

a four-bit field to indicate a specific source register or destination vector register for certain instructions other than the insert instruction, the four-bit field set to 1111 in the insert instruction to indicate that the four-bit field does not encode an operand.

29. The non-transitory machine-readable medium of claim 21 further comprising program code to cause the machine to perform the operation of:

performing address generation for the insert instruction using a scale, index, and base (SIB) byte of the insert instruction.

30. The non-transitory machine-readable medium of claim 21 further comprising program code to cause the machine to perform the operation of:

performing address generation for the insert instruction using a displacement factor byte of the insert instruction.