Storage device including a snooper that monitors a system bus to detect completion of writing data to a buffer memory and a method thereof

• US 10,459,854 B2
• Filed: 12/13/2017
• Issued: 10/29/2019
• Est. Priority Date: 03/10/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, JunBum
• Primary Examiner(s): Phan, Raymond N
• Application Number:
  US15/840,374
• Publication Number:
  US 20180260343A1
• Time in Patent Office: 685 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2213/28 DMA

Abstract

A memory controller according to example embodiments of the inventive concept includes a system bus, a first direct memory access (DMA) engine configured to write data in a buffer memory through the system bus, a snooper configured to output notification information indicating whether the data is stored in the buffer memory by snooping around the system bus, and a second direct memory access (DMA) engine configured to transmit the data written in the buffer memory to a host in response to the notification information from the snooper.

Claims

1. A memory controller comprising:

a system bus;

a first direct memory access (DMA) engine configured to receive a first data through the system bus and to write the first data in a buffer memory through the system bus;

a snooper configured to monitor the system bus to detect a completion of writing the first data into the buffer memory and to output notification information based on a detecting result on condition of detecting the completion; and

a second direct memory access (DMA) engine configured to transmit the first data written in the buffer memory to a host in response to the notification information from the snooper.

2. The memory controller of claim 1, wherein the first DMA is further configured to write a first meta data corresponding to the first data into the buffer memory after writing the first data into the buffer memory.

3. The memory controller of claim 1, wherein the first data comprises a plurality of sub data, and the first DMA engine is configured to write a plurality of meta data, each of the plurality of meta data corresponds to each of the plurality of sub data in the buffer memory.

4. The memory controller of claim 1, wherein the second DMA engine is configured to transmit the first data written in the buffer memory to the host in response to the notification information.

5. The memory controller of claim 1, further comprising:

a first interface configured to communicate with a nonvolatile memory device and to receive the first data from the nonvolatile memory device, and

a second interface configured to communicate with the host and to transmit the first data to the host,

wherein the first DMA engine is configured to write the first data received through the first interface in the buffer memory, and

wherein the second DMA engine is configured to transmit the first data to the host through the second interface.

6. The memory controller of claim 1, further comprising:

a processor performing an initial setting with respect to the first DMA engine and the second DMA engine in response to a request from the host.

7. The memory controller of claim 1, further comprising:

a buffer controller configured to be connected to the system bus and to control the buffer memory according to a control of the first DMA engine and the second DMA engine.

8. The memory controller of claim 2, wherein the snooper is configured to detect completion of writing the first data into the buffer memory by detecting the first meta data being transmitted to the buffer memory through the system bus.

9. The memory controller of claim 3, wherein the snooper is configured to detect the completion of writing the first data into the buffer memory on condition of detecting a specific number of meta data being written in the buffer memory.

10. The memory controller of claim 6, wherein the first DMA engine is configured to write the first data in the buffer memory without intervention of the processor after being initially set by the processor, and

wherein the second DMA engine is configured to transmit the first data from the buffer memory to the host without intervention of the processor after being initially set by the processor.

11. The memory controller of claim 9, wherein the second DMA engine is configured to transmit a first sub data among the plurality of sub data to the host in response to the notification information, the first sub data corresponding to a first meta data among the plurality of meta data written in the buffer memory.

12. A storage device, comprising:

a nonvolatile memory device;

a memory controller configured to transmit a first data stored in the nonvolatile memory device to a host according to a request of the host; and

a buffer memory device configured to temporarily store the first data according to a control of the memory controller,

wherein the memory controller includes,

a system bus,

a first direct memory access (DMA) engine configured to write the first data from the nonvolatile memory device in the buffer memory device, the first data being transmitted to the buffer memory device through the system bus,

a snooper configured to monitor the system bus to detect a completion of writing the first data into the buffer memory device and to output notification information indicating that the first data is stored in the buffer memory device on condition of detecting the completion, and

a second direct memory access (DMA) engine configured to transmit the first data written in the buffer memory device to the host in response to the notification information from the snooper.

13. The storage device of claim 12, wherein the memory controller further includes a processor configured to initially set the first and second DMA engines according to the request of the host.

14. The storage device of claim 12, wherein the second DMA engine is configured to transmit the first data written in the buffer memory device to the host without performing a periodic polling operation on the buffer memory device in response to the notification information.

15. The storage device of claim 13, wherein the first DMA engine is configured to write the first data in the buffer memory device without intervention of the processor after being initially set by the processor, and

wherein the second DMA engine is configured to transmit the first data from the buffer memory device to the host without intervention of the processor after being initially set by the processor.

16. A method of operating a storage device, the method comprising:

receiving a first data from a nonvolatile memory device through a system bus;

writing the first data into a buffer memory by a first direct memory access (a first DMA);

causing a snooper to monitor the system bus to detect a completion of writing the first data into the buffer memory and to output notification information on condition of detecting the completion; and

transmitting the first data stored in the buffer memory to a host by a second direct memory access (a second DMA) in response to the notification information.

17. The method of claim 16, wherein the notification information is outputted immediately after completing the writing the first data into the buffer memory.

18. The method of claim 17, wherein transmitting the first data to the host is performed by the second DMA without delay from receiving the notification information.

19. The method of claim 18, wherein transmitting the first data to the host is performed without periodical polling operation by the second DMA.

20. The method of claim 19, wherein the method further includes writing a first meta data corresponding to the first data after writing the first data into the buffer memory and transmitting the first meta data to the host after transmitting the first data to the host.