Load reduced nonvolatile memory interface
First Claim
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1. A system, comprising:
- a group of nonvolatile memory (NVM) devices;
a storage controller coupled to the group of NVM devices via a command bus, the storage controller to manage reading and writing to the NVM devices through one or more commands on the command bus; and
a data buffer coupled between the group of NVM devices and the storage controller on a data bus, the data buffer coupled to the storage controller via a control signal line separate from the command bus, the control signal line not provided to the NVM devices, the data buffer to re-drive data signals on the data bus for data corresponding to a command on the command bus,wherein the storage controller is to first send the command to the group of NVM devices on the command bus, bypassing the data buffer, and send a control signal to the data buffer on the control signal line, wherein the control signal is to trigger the data buffer to transfer the data signals between the group of NVM devices and the storage controller to synchronize the data signals to a clock signal for the command on the command bus.
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Abstract
A storage circuit includes a buffer coupled between the storage controller and the nonvolatile memory devices. The circuit includes one or more groups of nonvolatile memory (NVM) devices, a storage controller to control access to the NVM device, and the buffer. The buffer is coupled between the storage controller and the NVM devices. The buffer is to re-drive signals on a bus between the NVM devices and the storage controller, including synchronizing the signals to a clock signal for the signals. The circuit can include a data buffer, a command buffer, or both.
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Citations
20 Claims
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1. A system, comprising:
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a group of nonvolatile memory (NVM) devices; a storage controller coupled to the group of NVM devices via a command bus, the storage controller to manage reading and writing to the NVM devices through one or more commands on the command bus; and a data buffer coupled between the group of NVM devices and the storage controller on a data bus, the data buffer coupled to the storage controller via a control signal line separate from the command bus, the control signal line not provided to the NVM devices, the data buffer to re-drive data signals on the data bus for data corresponding to a command on the command bus, wherein the storage controller is to first send the command to the group of NVM devices on the command bus, bypassing the data buffer, and send a control signal to the data buffer on the control signal line, wherein the control signal is to trigger the data buffer to transfer the data signals between the group of NVM devices and the storage controller to synchronize the data signals to a clock signal for the command on the command bus. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A solid state drive (SSD), comprising:
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a storage controller including an interface to couple to a host processor, the storage controller to manage read and write requests from the host processor; and multiple storage circuits coupled to the storage controller via a command bus and via a data bus separate from the command bus, including a plurality of nonvolatile memory (NVM) devices; and a data buffer coupled between the plurality of NVM devices and the storage controller on the data bus, the data buffer coupled to the storage controller via a control signal line separate from the command bus, the control signal line not provided to the NVM devices, the data buffer to re-drive data signals on the data bus for data corresponding to a command on the command bus, wherein the storage controller is to first send the command to the plurality of NVM devices on the command bus, bypassing the data buffer, and send a control signal to the data buffer on the control signal line, wherein the control signal is to trigger the data buffer to transfer the data signals between the plurality of NVM devices and the storage controller to synchronize the data signals to a clock signal for the command on the command bus. - View Dependent Claims (12, 13, 14, 15)
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16. A method for data access, comprising:
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receiving a buffer command via a control signal line at a data buffer coupled between a group of nonvolatile memory (NVM) devices and a storage controller, the buffer command to be issued after a data access command issued to the group of NVM devices via a command signal bus separate from the control signal line, the data access command bypassing the data buffer; and responsive to receiving the buffer command, re-driving data signals on a data bus between the NVM devices and the storage controller, including synchronizing the data signals to a clock signal for the data access command on the command bus. - View Dependent Claims (17, 18, 19, 20)
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Specification