System and method for anti reverse engineering for analog integrated circuit

• US 10,460,061 B2
• Filed: 10/03/2017
• Issued: 10/29/2019
• Est. Priority Date: 10/03/2017
• Status: Active Grant

• Current Assignee: Ipgreat Incorporated
• Original Assignee: Ipgreat Incorporated
• Inventors: Chao, Yuan-Ju, Chu, Ta-Shun
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US15/723,239
• Publication Number:
  US 20190102502A1
• Time in Patent Office: 756 Days
• Field of Search: 716100, 716112, 716113, 716118, 716119
• CPC Class Codes: G06F 2117/06 Spare resources, e.g. for permanent fault suppression
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/573 using passive means
• CPC Class Codes: H01L 23/576 using active circuits

Abstract

Systems and methods of restraining reverse engineering process for analog integrated circuit use techniques of adding dummy devices, device fragmentation, increasing bus width, employing different layouts for the same circuit element and mixing different types of passive devices increase complexity and makes the layout floorplan more difficult to be extracted for the reverse engineering. The system adds dummy devices and ensures the extra devices and capacitance do not affect the target circuit performance.

Claims

1. A method for designing an integrated circuit (IC), comprising:

adding anti-reverse engineering for the IC by expanding complexity of one or more circuits or disguising a selected circuit;

checking if a functional block is an open-loop static circuitry and adding dummy devices on signal nets for open loop static circuits and otherwise separating static signals from dynamic signals and adding dummy devices on static signals; and

rendering a layout of the IC with the anti-reverse engineering design.

2. The method of claim 1, wherein the expanding complexity comprises adding one or more dummy devices.

3. The method of claim 2, comprising inserting the dummy devices in a middle in addition to placing the dummy devices on one or more sides of one or more functional devices of the IC.

4. The method of claim 1, wherein the expanding the complexity comprises device fragmentation.

5. The method of claim 4, comprising implementing an analog circuit floorplan to resemble a digital circuitry layout format by using multiple small device layouts.

6. The method of claim 4, wherein active devices are broken down into multiple smaller devices to add complexity against reverse engineering.

7. The method of claim 4, wherein passive devices including resistors or capacitors are implemented by a bank of multiple resistors or capacitors in parallel or in serial format to add complexity against reverse engineering.

8. The method of claim 1, comprising disguising a circuit by increasing a bus width.

9. The method of claim 8, wherein the bus signal width of circuitry is increased with inserted dummy signals to add complexity and restrain reverse engineering.

10. The method of claim 1, wherein the circuit disguise employs different layouts for the same circuit element.

11. The method of claim 10, wherein different layout realizations are used for the same circuit to misguide the reverse engineering.

12. The method of claim 1, wherein the circuit disguise mixes different types of passive devices.

13. The method of claim 12, wherein forming a resistor or a capacitor by using different type of resistors or capacitors to mislead the reverse engineering process intentionally.

14. The method of claim 1, comprising adding dummy devices to reinforce a target circuit, and meeting a predetermined performance with added devices and associated extra capacitance of the dummy devices.

15. The method of claim 14, wherein the dummy devices are added based on the criteria of static circuit or dynamic circuit.

16. The method of claim 14, wherein the signals of circuits are categorized into static signals and dynamic signals, further comprising adding dummy devices on the static signals and only selected dynamic signals.

17. The method of claim 1, comprising fabricating the IC.

18. A system to design an integrated circuit (IC), comprising:

a processor to receive an IC design with one or more circuits thereon;

code for adding anti-reverse engineering for the IC by expanding a complexity of one or more circuits or disguising a selected circuit;

code for checking if a functional block is an open-loop static circuitry and adding dummy devices on signal nets for open loop static circuits and otherwise separating static signals from dynamic signals and adding dummy devices on static signals; and

code for rendering a layout of the IC with the anti-reverse engineering design.

19. An integrated circuit, comprising:

a plurality of functioning circuits on a substrate;

a disguised circuit on the substrate or one or more complexity adding circuits on the substrate to foil piracy by checking if a functional block is an open-loop static circuitry and adding dummy devices on signal nets for open loop static circuits and otherwise separating static signals from dynamic signals and adding dummy devices on static signals; and

,

wherein the disguised circuit or the complexity adding circuit meets a predetermined performance with added devices and associated extra capacitance of the dummy devices.

20. The IC of claim 19, wherein the signals of circuitry are categorized into static signals and dynamic signals, further comprising adding dummy devices on the static signals and only selected dynamic signals.