Semiconductor device and display apparatus

• US 10,460,654 B2
• Filed: 12/17/2014
• Issued: 10/29/2019
• Est. Priority Date: 03/06/2014
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: Ishii, Hiroaki
• Primary Examiner(s): Patel, Nitin
• Assistant Examiner(s): Stone, Robert M
• Application Number:
  US15/123,087
• Publication Number:
  US 20170076662A1
• Time in Patent Office: 1,777 Days
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 2370/14 Use of low voltage differential signaling [LVDS] for display data communication
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players

Abstract

A semiconductor device includes: a receiving circuit which receives communication frames each transmitted with a first period or a second period that are different from each other and including a synchronization code and data; a logic circuit which has a first operation state in which the received communication frames are each processed as data other than a digital video signal, and a second operation state in which the received communication frames are each processed as the digital video signal; a detecting circuit which detects the synchronization code from each of the received communication frames; a measuring circuit which measures a period of the detected synchronization code; and a determining circuit which determines the measured period. The logic circuit substantially makes a transition to the first operation state or the second operation state according to a result of the determining.

Claims

1. A semiconductor device which controls display of a display panel, the semiconductor device comprising:

a receiving circuit which receives a plurality of communication frames,

each of the plurality of communication frames

being transmitted with a first period or a second period different from the first period, and

including a synchronization code and data;

a logic circuit configured to operate in two operation states, the two operation states including a first operation state and a second operation state,

in the first operation state, one or more communication frames of the first period received by the receiving circuit are each processed as data other than a digital video signal, wherein the data other than the video signal include control data from the semiconductor device and dummy data attached to a payload of a respective communication frame of the one or more communication frames, and

in the second operation state, one or more communication frames of the second period received by the receiving circuit are each processed as the digital video signal;

a detecting circuit which detects the synchronization code from each of the plurality of communication frames received by the receiving circuit;

a measuring circuit which measures a period of the synchronization code detected in each of the plurality of communication frames, the period of the synchronization code either corresponding to the first period or the second period; and

a determining circuit which determines whether the period of the synchronization code measured corresponds to the first period or the second period, wherein

the logic circuit transitions to the first operation state or the second operation state based on whether the period of the synchronization code measured corresponds to the first period or the second period,

wherein the receiving circuit receives at least one frame in a previous operation state even after an operation state has been changed to a new operation state at the receiving circuit.

2. The semiconductor device according to claim 1, wherein

the semiconductor device receives a notification from outside, the notification instructing a transition to the first operation state or a transition to the second operation state,

when the notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit indicates the first period, the logic circuit transitions to the first operation state, and

when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit indicates the second period, the logic circuit transitions to the second operation state.

3. The semiconductor device according to claim 1, wherein

when a notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit does not indicate the first period, the logic circuit discards, without processing, the plurality of communication frames received by the receiving circuit, and

when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit does not indicate the second period, the logic circuit discards, without processing, the plurality of communication frames received by the receiving circuit.

4. The semiconductor device according to claim 1, wherein

the semiconductor device controls (i) a row-drive circuit which drives the display panel including a plurality of pixels arranged in rows and columns, on a pixel-row basis, and (ii) a column-drive circuit which drives the display panel on a pixel-column basis.

5. The semiconductor device according to claim 1, wherein

the semiconductor device is a field programmable gate array (FPGA).

6. The semiconductor device according to claim 1, wherein

when, an instruction to transition from the first operation state to the second operation state is received by the logic circuit during processing of the communication frames in the first operation state, the logic circuit discards, without processing, communication frames of the first operation state received after receiving of the instruction to switch to the second operation state.

7. The semiconductor device according to claim 6, wherein

when, an instruction to transition from the second operation state to the first operation state is received by the logic circuit during processing of the communication frames in the second operation state, the logic circuit discards, without processing, communication frames of the second operation state received after receiving of the instruction to switch to the first operation state.

8. A display apparatus comprising:

a first semiconductor chip that is the semiconductor device according to claim 1;

a second semiconductor chip which transmits the plurality of communication frames unidirectionally to the first semiconductor chip;

a microcomputer which outputs, to the first semiconductor chip and the second semiconductor chip, a notification instructing a transition to the first operation state or a transition to the second operation state;

a display panel including a plurality of pixels arranged in rows and columns;

a row-drive circuit which is controlled by the first semiconductor chip and drives a pixel row of the display panel; and

a column-drive circuit which is controlled by the first semiconductor chip and drives a pixel column of the display panel, wherein

the second semiconductor chip transmits the plurality of communication frames with the first period after receiving the notification instructing the transition to the first operation state, and transmits the plurality of communication frames with the second period after receiving the notification instructing the transition to the second operation state.

9. The display apparatus according to claim 8, wherein

when the notification received last instructs the transition to the first operation state, and the result of the determining performed by the determining circuit indicates the first period, the logic circuit transitions to the first operation state, and

when the notification received last instructs the transition to the second operation state, and the result of the determining performed by the determining circuit indicates the second period, the logic circuit transitions to the second operation state.