Display panel and display device

• US 10,460,656 B2
• Filed: 02/28/2018
• Issued: 10/29/2019
• Est. Priority Date: 09/08/2017
• Status: Active Grant

• Current Assignee: Wuhan Tianma Micro-Electronics Company Limited (Wuhan Donghu New Technology Development Zone Production Promotion Centre), Wuhan Tianma Microelectronics Company Limited Shanghai Branch
• Original Assignee: Shanghai Tianma AM-OLED Co. Ltd (Tianma Microelectronics Company Limited)
• Inventors: Xi, Kerui, Cui, Tingting, Zhu, Juan
• Primary Examiner(s): Karimi, Pegeman
• Application Number:
  US15/907,288
• Publication Number:
  US 20180190190A1
• Time in Patent Office: 608 Days
• CPC Class Codes: G09G 2300/0413 Details of dummy pixels or dummy lines in flat panels
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0281 Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3225 using an active matrix
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays

Abstract

Disclosed are a display panel and a display device. A middle area is arranged between the first subarea and the second subarea so that components such as a camera and a receiver can be arranged at corresponding positions in the middle area. First driving signal lines only extend along the row direction of the pixels to the edge of the first subarea close to the middle area and second driving signal lines only extend to the edge of the second subarea close to the middle area. A first driving circuit is arranged in the first subarea to drive the first driving signal lines to operate and a second driving circuit is arranged in the second subarea to drive the second driving signal lines to operate.

Claims

1. A display panel, comprising:

a first area and a second area, wherein the first area comprises a middle area, a first subarea and a second subarea, the first subarea and the second subarea are separated by the middle area;

the first subarea comprises at least two pixels, one or more first driving signal lines extending in a row direction of the pixels and a first driving circuit;

wherein one end of at least one of the first driving signal lines is electrically connected to the first driving circuit and the other end of the first driving signal line extends to an edge of the first subarea close to the middle area; and

the first driving circuit is configured to drive the first driving signal lines located in the first subarea;

the second subarea comprises at least two pixels, one or more second driving signal lines extending in the row direction of the pixels and a second driving circuit;

wherein one end of at least one of the second driving signal lines is electrically connected to the second driving circuit and the other end of the second driving signal line extends to an edge of the second subarea close to the middle area; and

the second driving circuit is configured to drive the second driving signal lines located in the second subarea;

wherein the first driving circuit comprises at least two cascaded first shift register units, wherein each of the first shift register units is respectively electrically connected with a first clock signal line, a first reference voltage signal line and at least one first driving signal line correspondingly, and an input signal terminal of a first-stage first shift register unit is connected to a first initial signal terminal, and an input signal terminal of each of other stages of first shift register units is connected to a driving signal output terminal of its adjacent previous stage of first shift register unit; and

the second driving circuit comprise at least two cascaded second shift register units, wherein each of the second shift register units is respectively electrically connected with a second clock signal line, a second reference voltage signal line and at least one second driving signal line correspondingly, and an input signal terminal of a first-stage second shift register unit is connected to a second initial signal terminal, and an input signal terminal of each of other stages of second shift register units is respectively connected to a driving signal output terminal of its adjacent previous stage of second shift register unit;

wherein the first subarea further comprises at least two first connecting lines insulated from each other;

or the second subarea further comprises at least two second connecting lines insulated from each other;

in the first subarea, one end of each of at least two first driving signal lines is correspondingly electrically connected to a same first shift register unit, and the other ends of the at least two first driving signal lines are electrically connected via one first connecting line;

in the second subarea, one end of each of at least two second driving signal lines is correspondingly electrically connected to a same second shift register unit, and the other ends of the at least two second driving signal lines are electrically connected via one second connecting line.

2. The display panel according to claim 1, wherein the first shift register units located in the first subarea correspond to the second shift register units located in the second subarea in a one to one relationship and a first shift register unit and a second shift register unit which are correspondingly arranged simultaneously output a same driving signal.

3. The display panel according to claim 2, further comprising a first wire, the first initial signal terminal and the second initial signal terminal being electrically connected with each other through the first wire.

4. The display panel according to claim 3, further comprising at least two second wires and at least two third wires, the second wires and the third wires both insulated from the first wires and the second wires insulated from the third wires;

clock control signal lines with a same period and a same phase in the first clock control signal line and in the second clock control signal line are electrically connected to each other through one second wire; and

reference voltage signal lines of a same voltage in the first reference voltage signal line and the second reference voltage signal line are electrically connected to each other through one third wire.

5. The display panel according to claim 4, wherein the first wire, the second wires and the third wires are all arranged along an edge of the first subarea, an edge of the second subarea and an edge of the second area close to the middle area.

6. The display panel according to claim 4, wherein the first shift register units and the second shift register units each comprise at least two switching transistors,

wherein

each of the pixels comprises a light-emitting element and a pixel compensation circuit electrically connected to the light-emitting element;

the pixel compensation circuit at least comprises a storage capacitor;

at least one kind of the first wire, the second wire and the third wire is made of a same material and configured at a same layer as gates of the switching transistors;

or, at least one kind of the first wire, the second wire and the third wire is made of a same material and configured at a same layer as one terminal of the storage capacitor;

or,

at least one kind of the first wire, the second wire and the third wire is made of a same material and configured at a same layer as sources and drains of the switching transistors.

7. The display panel according to claim 4, wherein each of the pixels comprises a light-emitting element and a pixel compensation circuit electrically connected to the light-emitting element;

the light-emitting element comprises an anode, an electroluminescent layer and a cathode that are stacked one above another;

at least one kind of the first wire, the second wire and the third wire is made of a same material and configured at a same layer as the anode;

the display panel further comprises non-display dummy pixels at a part of an edge of the first subarea and at a part of an edge of the second subarea; and

an orthographic projection of at least one kind of the first wire, the second wire and the third wire on the display panel and an orthographic projection of the non-display dummy pixels on the display panel overlap.

8. The display panel according to claim 1, wherein each of the pixels comprises a light-emitting element and a pixel compensation circuit electrically connected to the light-emitting element;

the pixel compensation circuit at least comprises a storage capacitor;

the first shift register units and the second shift register units each comprise at least two switching transistors;

when the display panel comprises at least two first connecting lines, the first connecting lines are made of a same material and configured at a same layer as sources and drains of the switching transistors;

or the first connecting lines are made of a same material and configured at a same layer as one terminal of the storage capacitor;

or,

when the display panel comprises at least two second connecting lines, the second connecting lines are made of a same material and configured at a same layer as sources and drains of the switching transistors;

or the second connecting lines are made of a same material and configured at a same layer as one terminal of the storage capacitor;

or

when the first subarea comprises at least two first connecting lines, the first connecting lines and the first driving signal lines are made of a same material and configured at a same layer;

or

when the second subarea comprises at least two second connecting lines, the second connecting lines and the second driving signal lines are made of a same material and configured at a same layer.

9. The display panel according to claim 1, wherein each of the pixels comprises a light-emitting element and a pixel compensation circuit electrically connected to the light-emitting element;

the light-emitting element comprises an anode, an electroluminescent layer and a cathode that are stacked one above another;

when the display panel comprises at least two first connecting lines, the first connecting lines and the anode are made of a same material and configured at a same layer;

or

when the display panel comprises at least two second connecting lines, the second connecting lines and the anode are made of a same material and configured at a same layer;

the display panel further comprises non-display dummy pixels at least at an edge of the first subarea close to the middle area and at an edge of the second subarea close to the middle area; and

when the first subarea comprises at least two first connecting lines, orthographic projections of the first connecting lines on the display panel overlap orthographic projections of non-display dummy pixels located at the edge of the first subarea close to the middle area on the display panel;

or

when the second subarea comprises at least two second connecting lines, orthographic projections of the second connecting lines on the display panel overlap orthographic projections of non-display dummy pixels located at the edge of the second subarea close to the middle area on the display panel.

10. The display panel according to claim 1, wherein when the first subarea comprises at least two first connecting lines, the first subarea further comprises at least two first electrostatic discharge circuits, and each of the first connecting lines is correspondingly electrically connected to one first electrostatic discharge circuit;

when the second subarea comprises at least two second connecting lines, the second subarea further comprises at least two second electrostatic discharge circuits, and each of the second connecting lines is correspondingly electrically connected to one second electrostatic discharge circuit.

11. The display panel according to claim 1, wherein each of the first shift register units is located on a same side of the first subarea and each of the second shift register units is located on a same side of the second subarea.

12. The display panel according to claim 11, wherein the first shift register units are located at a side of the first subarea away from the middle area and the second shift register units are located at a side of the second subarea away from the middle area.

13. The display panel according to claim 1, wherein the second area comprises at least two pixels, a third driving signal line extending along the row direction of the pixels, and a third driving circuit electrically connected with the third driving signal line, wherein the third driving circuit is configured to drive the third driving signal line.

14. The display panel according to claim 13, wherein the third driving circuit comprises at least two cascaded third shift register units, wherein each of the third shift register units is respectively electrically connected with a third clock signal line, a third reference voltage signal line and at least one third driving signal line correspondingly;

an input signal terminal of a first-stage third shift register unit is connected to a third initial signal terminal, and an input signal terminal of each of other stages of third shift register units is respectively connected to driving a signal output terminal of its adjacent previous stage of third shift register unit.

15. The display panel according to claim 14, wherein the third initial signal terminal is an independent initial signal terminal;

and an initial signal of the third initial signal terminal is different from initial signals of the first initial signal terminal and the second initial signal terminal.

16. The display panel according to claim 14, wherein an input signal terminal of a first-stage third shift register unit is electrically connected to a driving signal output terminal of a last-stage first shift register unit in the first driving circuit;

or

the input signal terminal of the first-stage third shift register unit is electrically connected to a driving signal output terminal of a last-stage second shift register unit in the second driving circuit.

17. The display panel according to claim 14, wherein the second area comprises two third driving circuits which are electrically connected to two ends of the third driving signal lines respectively;

third shift register units in the two third driving circuits are arranged in a one-to-one corresponding relationship and third shift register units which are arranged correspondingly output a same driving signal at the same time.

18. The display panel according to claim 17, wherein the third driving signal lines in the second area are disconnected at a same gap between two adjacent columns of pixels to form first driving sub-signal lines and second driving sub-signal lines insulated from each other;

one end of each of the first driving sub-signal lines is electrically connected to one of the two third driving circuits, and the other end of each of the first driving sub-signal lines extends to the gap;

one end of each of the second driving sub-signal lines is electrically connected to the other one of the two third driving circuits, and the other end of each of the second driving sub-signal lines extends to the gap;

one end of each of at least two first driving sub-signal lines is electrically connected to a same third shift register unit, and the second area further comprises at least two third connecting lines, wherein the other ends of the first driving sub-signal lines connected to the same third shift register unit are electrically connected to each other via one third connecting line;

or,

one end of each of at least two second driving sub-signal lines is electrically connected to a same third shift register unit, and the second area further comprises at least two fourth connecting lines, wherein the other ends of the second driving sub-signal lines connected to the same third shift register unit are electrically connected to each other via one fourth connecting line.

19. The display panel according to claim 1, wherein the first driving signal lines and the second driving signal lines each comprise a gate line, the first driving circuit comprises a first gate driving circuit, and the second driving circuit comprises a second gate driving circuit;

or,

the first driving signal lines and the second driving signal lines each comprise a light emitting control signal line, the first driving circuit comprises a first light emitting driving circuit, and the second driving circuit comprises a second light emitting driving circuit.

20. The display panel according to claim 1, further comprising a substrate on which the pixels are arranged, the middle area being a hollow area of the subarea;

or

an outline of the middle area is a rectangle, or the outline of the middle area is special-shaped.

21. A display device, comprising:

the display panel according to claim 1,

the display device further comprises one or a combination of a camera, a receiver, a light sensor, a distance sensor, an iris recognition sensor and a fingerprint recognition sensor;

an orthographic projection of one or a combination of the camera, the receiver, the light sensor, the distance sensor, the iris recognition sensor and the fingerprint recognition sensor in the display device on the display panel is located within the orthographic projection of the middle area on the display panel.

22. A display panel, comprising:

a first area and a second area, wherein the first area comprises a middle area, a first subarea and a second subarea, the first subarea and the second subarea are separated by the middle area;

the first subarea comprises at least two pixels, one or more first driving signal lines extending in a row direction of the pixels and a first driving circuit wherein one end of at least one of the first driving signal lines is electrically connected to the first driving circuit and the other end of the first driving signal line extends to an edge of the first subarea close to the middle area; and

the first driving circuit is configured to drive the first driving signal lines located in the first subarea;

the second subarea comprises at least two pixels, one or more second driving signal lines extending in the row direction of the pixels and a second driving circuit wherein one end of at least one of the second driving signal lines is electrically connected to the second driving circuit and the other end of the second driving signal line extends to an edge of the second subarea close to the middle area; and

the second driving circuit is configured to drive the second driving signal lines located in the second subarea;

wherein the first driving signal lines and the second driving signal lines each comprise a gate line, the first driving circuit comprises a first gate driving circuit, and the second driving circuit comprises a second gate driving circuit or,

the first driving signal lines and the second driving signal lines each comprise a light emitting control signal line, the first driving circuit comprises a first light emitting driving circuit, and the second driving circuit comprises a second light emitting driving circuit;

wherein when the first driving signal lines and the second driving signal lines each comprise a gate line, the second area comprises a gate line and two third gate driving circuits which are connected to two ends of the gate line in the second area respectively;

the first gate driving circuit is connected to one end of the gate line in the first subarea away from the middle area;

the second gate driving circuit is connected to one end of the gate line in the second subarea away from the middle area.

23. A display panel, comprising:

a first area and a second area, wherein the first area comprises a middle area, a first subarea and a second subarea, the first subarea and the second subarea are separated by the middle area;

the first subarea comprises at least two pixels, one or more first driving signal lines extending in a row direction of the pixels and a first driving circuit wherein one end of at least one of the first driving signal lines is electrically connected to the first driving circuit and the other end of the first driving signal line extends to an edge of the first subarea close to the middle area; and

the first driving circuit is configured to drive the first driving signal lines located in the first subarea;

the second subarea comprises at least two pixels, one or more second driving signal lines extending in the row direction of the pixels and a second driving circuit wherein one end of at least one of the second driving signal lines is electrically connected to the second driving circuit and the other end of the second driving signal line extends to an edge of the second subarea close to the middle area; and

the second driving circuit is configured to drive the second driving signal lines located in the second subarea;

wherein the first driving signal lines and the second driving signal lines each comprise a gate line, the first driving circuit comprises a first gate driving circuit, and the second driving circuit comprises a second gate driving circuit or,

the first driving signal lines and the second driving signal lines each comprise a light emitting control signal line, the first driving circuit comprises a first light emitting driving circuit, and the second driving circuit comprises a second light emitting driving circuit;

wherein when the first driving signal line and the second driving signal line each comprise a light emitting control signal line, the second area comprises a light emitting control signal line and two third light emitting driving circuits which are connected to two ends of the light emitting control signal lines in the second area respectively;

the first light emitting driving circuit is connected to one end of the light emitting control signal line in the first subarea away from the middle area;

the second light emitting driving circuit is connected to one end of the light emitting control signal lines in the second subarea away from the middle area.

24. A display panel, comprising:

a first area and a second area, wherein the first area comprises a middle area, a first subarea and a second subarea, the first subarea and the second subarea are separated by the middle area;

the first subarea comprises at least two pixels, one or more first driving signal lines extending in a row direction of the pixels and a first driving circuit wherein one end of at least one of the first driving signal lines is electrically connected to the first driving circuit and the other end of the first driving signal line extends to an edge of the first subarea close to the middle area; and

the first driving circuit is configured to drive the first driving signal lines located in the first subarea;

the second subarea comprises at least two pixels, one or more second driving signal lines extending in the row direction of the pixels and a second driving circuit wherein one end of at least one of the second driving signal lines is electrically connected to the second driving circuit and the other end of the second driving signal line extends to an edge of the second subarea close to the middle area; and

the second driving circuit is configured to drive the second driving signal lines located in the second subarea;

the display panel further comprising non-display dummy pixels at least at an edge of the first subarea close to the middle area and at least at an edge of the second subarea close to the middle area.