Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank

• US 10,460,781 B2
• Filed: 12/27/2017
• Issued: 10/29/2019
• Est. Priority Date: 09/27/2016
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Berger, Neal, Louie, Benjamin, El-Baraji, Mourad, Crudele, Lester, Hillman, Daniel
• Primary Examiner(s): Byrne, Harry W
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US15/855,948
• Publication Number:
  US 20180122446A1
• Time in Patent Office: 671 Days
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

A memory device for storing data is disclosed. The memory device comprises a memory bank comprising a memory array of addressable memory cells and a pipeline configured to process read and write operations addressed to the memory bank. Further, the memory device comprises an x decoder circuit coupled to the memory array for decoding an x portion of a memory address for the memory array and a y multiplexer circuit coupled to the memory array and operable to simultaneously multiplex across the memory array based on two y portions of memory addresses and, based thereon with the x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of the memory array, wherein the x decoder and the y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to the memory array.

Claims

1. A memory device for storing data, the memory device comprising:

a memory bank comprising a memory array of addressable memory cells;

a pipeline configured to process read and write operations addressed to said memory bank;

an x decoder circuit coupled to said memory array for decoding an x portion of a memory address for said memory array; and

a y multiplexer circuit coupled to said memory array and operable to simultaneously multiplex across said memory array based on two y portions of memory addresses and, based thereon with said x portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array, and

wherein said x decoder and said y multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.

2. A memory device as described in claim 1 wherein said x decoder is operable to assert a row line of said memory array and wherein said two separate memory cells share said row line in common.

3. A memory device as described in claim 1 wherein said read port and said write port allow a write operation and a read-verify operation, that share a common row, to simultaneously access said memory array.

4. A memory device as described in claim 1 wherein said read port and said write port allow a write operation and a read-verify operation, that share a common row and that have different y portions, to simultaneously access said memory array.

5. A memory device as described in claim 1 wherein said addressable memory cells comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells.

6. A memory device as described in claim 1 wherein said x portion of said memory address decodes to a common row line shared by said two separate memory cells of said memory array and wherein further said two y portions of memory addresses respectively select first and second sets of bit lines associated with said two separate memory cells of said memory array.

7. A memory device as described in claim 1 further comprising a plurality of input/output channels, said plurality of input/output channels coupled to said y multiplexer circuit.

8. A memory device for storing data, the memory device comprising:

a memory bank comprising a memory array of addressable memory cells, wherein said addressable memory cells comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;

a pipeline configured to process read and write operations addressed to said memory bank, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage;

a row decoder circuit coupled to said memory array for decoding a row portion of a memory address and for asserting a row line of said memory array; and

a column multiplexer circuit coupled to said memory array and operable to simultaneously multiplex based on two column portions of memory addresses and, based thereon with said row portion, for simultaneously writing a value and reading a value associated with two separate memory cells of said memory array,

wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.

9. A memory device as described in claim 8 wherein said two separate memory cells share said row line in common and are in different columns within said memory array.

10. A memory device as described in claim 8 wherein said read port and said write port allow a write operation and a read-verify operation, that have addresses that share a common row portion but with different column portions, to simultaneously access said memory array.

11. A memory device as described in claim 9 wherein said row portion of said memory address is applied to said row line shared by said two separate memory cells of said memory array and wherein further said two column portions of memory addresses respectively select first and second sets of bit lines associated with said two separate memory cells of said memory array.

12. A memory device as described in claim 8 further comprising a plurality of input/output data channels, said plurality of input/output data channels coupled to said column multiplexer circuit.

13. A method of accessing a memory device, said method comprising:

processing read and write operations addressed to a memory bank using a pipeline, wherein said pipeline comprises a write pipestage followed by a verify-read pipestage and wherein further said memory bank comprises a memory array of addressable memory cells that comprise spin-transfer torque magnetic random access memory (STT-MRAM) cells;

decoding a row portion of a memory address and asserting a row line of said memory array using a row decoder circuit coupled to said memory array; and

simultaneously multiplexing column lines of said memory array based on two column portions of memory addresses and, based thereon with said row portion, simultaneously writing a value and reading a value associated with two separate memory cells of said memory array using a column multiplexer circuit coupled to said memory array, and

wherein said row decoder and said column multiplexer are implemented to provide a read port and a write port which are operable to simultaneously operate with respect to said memory array.

14. A method as described in claim 13 wherein said two separate memory cells share said row line in common and are in different columns of said memory array.

15. A method as described in claim 13 wherein said read port and said write port allow a write operation and a read-verify operation, that have addresses that share a common row portion but with different column portions, to simultaneously access said memory array.

16. A method as described in claim 13 wherein said row portion of said memory address is applied to said common row line shared by said two separate memory cells of said memory array and wherein further said two column portions of memory addresses respectively select first and second sets of bit lines associated with said two separate memory cells of said memory array.

17. A method as described in claim 13 wherein said column multiplexer circuit is coupled to a plurality of input/output data channels.