Systems and methods for generating stagger delays in memory devices
First Claim
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1. A logic circuit, configured to:
- receive a current signal from a resistor-capacitor (RC) circuit, wherein the current signal corresponds to data received by the RC circuit, wherein the output buffer is configured to be written or read via one or more memory banks;
determine a strength of the current signal;
transmit a first gate signal to a first set of switches configured to couple a voltage source to an output buffer configured to couple to the one or more memory banks in response to the strength being above a first threshold; and
transmit a second gate signal to a second set of switches configured to couple the voltage source to the output buffer in response to the strength being below the first threshold.
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Abstract
A semiconductor device may include a number of memory banks, an output buffer that couples to the memory banks, a number of switches that couple a voltage source to the output buffer, and a stagger delay circuit. The stagger delay circuit may include a resistor-capacitor (RC) circuit that outputs a current signal that corresponds to a data voltage signal received by the RC circuit. The stagger delay circuit may also include a logic circuit that determines a strength of the current signal and sends a first gate signal to a first portion of the switches based on the strength.
11 Citations
12 Claims
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1. A logic circuit, configured to:
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receive a current signal from a resistor-capacitor (RC) circuit, wherein the current signal corresponds to data received by the RC circuit, wherein the output buffer is configured to be written or read via one or more memory banks; determine a strength of the current signal; transmit a first gate signal to a first set of switches configured to couple a voltage source to an output buffer configured to couple to the one or more memory banks in response to the strength being above a first threshold; and transmit a second gate signal to a second set of switches configured to couple the voltage source to the output buffer in response to the strength being below the first threshold. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method, comprising:
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receiving, via a circuit, a current signal that corresponds to data to be written or read via one or more memory banks; transmit, via the circuit, a first gate signal to a first set of switches configured to couple a voltage source to an output buffer, wherein the output buffer is configured to couple to the one or more memory banks in response to the strength of the current signal being above a first threshold; transmit, via the circuit, a second gate signal to a second set of switches configured to couple the voltage source to the output buffer in response to the strength of the current signal being below the first threshold; and transmit, via the circuit, a third gate signal to a third set of switches configured to couple the voltage source to the output buffer in response to the strength being below a second threshold. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification