Memory device and programming operation method thereof with different bit line voltages
First Claim
1. An operation method for a memory device having a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the operation method for the memory device including:
- applying a program voltage to at least a selected word line of the word lines; and
during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, generating and applying a plurality of different bit line voltages to the selected bit lines;
the plurality of different bit line voltages generated and applied to the selected bit lines have different rising edges; and
in generating the different bit line voltages, the bit line voltage having an earliest rising edge and a highest bit line voltage is generated for applying to a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, and the plurality of the different bit line voltages are not corresponding to the program voltage.
1 Assignment
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Accused Products
Abstract
Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
12 Citations
13 Claims
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1. An operation method for a memory device having a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines, the operation method for the memory device including:
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applying a program voltage to at least a selected word line of the word lines; and during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, generating and applying a plurality of different bit line voltages to the selected bit lines;
the plurality of different bit line voltages generated and applied to the selected bit lines have different rising edges; and
in generating the different bit line voltages, the bit line voltage having an earliest rising edge and a highest bit line voltage is generated for applying to a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, and the plurality of the different bit line voltages are not corresponding to the program voltage. - View Dependent Claims (2, 3)
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4. An operation method for a memory device having a memory array including a plurality of word lines and a plurality of bit lines, the bit lines being grouped into a plurality of bit line groups based on respective locations of the bit lines on the word lines, the operation method for the memory device including:
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applying a program voltage to at least a selected word line of the word lines; and during a high level period of the program voltage, generating and applying a plurality of different bit line voltages to the selected bit line groups, wherein the plurality of different bit line voltages have different rising edges; and
a first selected bit line group of the selected bit line groups, which is closest to a head of the word lines, is applied with the bit line voltage having an earliest rising edge and a highest bit line voltage, and the plurality of the different bit line voltages are not corresponding to the program voltage. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A memory device, including:
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a memory array including a plurality of memory cells, a plurality of word lines and a plurality of bit lines; a control circuit coupled to the memory array; and an operation voltage generation circuit, coupled to the memory array and the control circuit, for generating a program voltage to at least a selected word line of the word lines of the memory array; wherein under control of the control circuit, during a high level period of the program voltage, based on respective locations of a plurality of selected bit lines of the bit lines on the word lines, the operation voltage generation circuit generates and applies a plurality of different bit line voltages to the selected bit lines;
the plurality of different bit line voltages have different rising edges; and
in generating the different bit line voltages, the bit line voltage having an earliest rising edge and a highest bit line voltage is generated for applying to a plurality of first selected bit lines of the selected bit lines, which are closest to a head of the word lines, and the plurality of the different bit line voltages are not corresponding to the program voltage. - View Dependent Claims (12, 13)
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Specification